From patchwork Fri Aug 29 14:47:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edward Nevill X-Patchwork-Id: 36303 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f71.google.com (mail-pa0-f71.google.com [209.85.220.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E47FC2054D for ; Fri, 29 Aug 2014 14:47:21 +0000 (UTC) Received: by mail-pa0-f71.google.com with SMTP id et14sf36604566pad.2 for ; Fri, 29 Aug 2014 07:47:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:message-id:subject:from:reply-to:to :cc:date:organization:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe:content-type :content-transfer-encoding; bh=OITk2ZB4F76pMRDKClji4kuUAhl/W+2kjAlQf9SUudE=; b=J7JqBu0OUD3ji2C8tKPSVe8m0m8uFn7O/l8HtKTC5XMpVNBcvCieJoCV8dNcNHQVKZ sGMdH2aoO+aJy5fU53gMMGb3rEayIlt5PWjiQCsPFvVwR7aDbQNk55e2WBzcuCYB+KmD Ngpnwa2kJpFiZ4pRU/IiTgsMYFxCn8H8r9cE2PBZ7N9sZ0RqrzCdm+v089ZC/Ybrhpxg ay7rmZ45T7lr8JQm1R33rZUwfBQwEcrdz8N0NZ45kVWX/nq6RoBxCQKTa4QrVBFb+TZ3 iCIr/GCEFE7SuavDL+ave9CQTp1deB1rJezxTrxxl2xCRmd0H6E3xo223ycWcIIAq6CL 2OmA== X-Gm-Message-State: ALoCoQmgSbtZXJ6FHFivMhobO9JE18VRm6uW+pbUMEQz8LFgxBuEua2ThWNYmVA25CwPtEjj8T6e X-Received: by 10.66.65.131 with SMTP id x3mr5479713pas.13.1409323641203; Fri, 29 Aug 2014 07:47:21 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.88.203 with SMTP id t69ls1060626qgd.30.gmail; Fri, 29 Aug 2014 07:47:21 -0700 (PDT) X-Received: by 10.220.105.201 with SMTP id u9mr10615142vco.11.1409323641096; Fri, 29 Aug 2014 07:47:21 -0700 (PDT) Received: from mail-vc0-f169.google.com (mail-vc0-f169.google.com [209.85.220.169]) by mx.google.com with ESMTPS id o8si214531vdw.92.2014.08.29.07.47.21 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 29 Aug 2014 07:47:21 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) client-ip=209.85.220.169; Received: by mail-vc0-f169.google.com with SMTP id hq11so2619237vcb.28 for ; Fri, 29 Aug 2014 07:47:21 -0700 (PDT) X-Received: by 10.52.119.229 with SMTP id kx5mr6852388vdb.40.1409323640952; Fri, 29 Aug 2014 07:47:20 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.45.67 with SMTP id uj3csp28044vcb; Fri, 29 Aug 2014 07:47:20 -0700 (PDT) X-Received: by 10.194.249.164 with SMTP id yv4mr14290677wjc.34.1409323639779; Fri, 29 Aug 2014 07:47:19 -0700 (PDT) Received: from mail-we0-f172.google.com (mail-we0-f172.google.com [74.125.82.172]) by mx.google.com with ESMTPS id gs3si347617wjc.113.2014.08.29.07.47.19 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 29 Aug 2014 07:47:19 -0700 (PDT) Received-SPF: pass (google.com: domain of edward.nevill@linaro.org designates 74.125.82.172 as permitted sender) client-ip=74.125.82.172; Received: by mail-we0-f172.google.com with SMTP id q59so2298756wes.17 for ; Fri, 29 Aug 2014 07:47:19 -0700 (PDT) X-Received: by 10.180.14.169 with SMTP id q9mr4362659wic.19.1409323638908; Fri, 29 Aug 2014 07:47:18 -0700 (PDT) Received: from [10.0.7.5] ([88.98.47.97]) by mx.google.com with ESMTPSA id ga9sm382300wjb.45.2014.08.29.07.47.17 for (version=SSLv3 cipher=RC4-SHA bits=128/128); Fri, 29 Aug 2014 07:47:18 -0700 (PDT) Message-ID: <1409323637.3470.15.camel@localhost.localdomain> Subject: RFR: Optimise store of 0 byte into card table From: Edward Nevill Reply-To: edward.nevill@linaro.org To: "aarch64-port-dev@openjdk.java.net" Cc: Patch Tracking Date: Fri, 29 Aug 2014 15:47:17 +0100 Organization: Linaro X-Mailer: Evolution 3.8.5 (3.8.5-2.fc19) Mime-Version: 1.0 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: edward.nevill@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Hi, The following patch optimises the storing of 0 bytes into the card table. Firstly the existing code was generating mov wS, zr stlrb wS, [xN] because it didn't have a rule for storing 0. This has been optimised to stlrb zr, [xN] Note: I have only done this optimisation for bytes, should I also do it for 16, 32 & 64 bit values? How often do these actually occur? Secondly, if the byte in memory is already 0 it skips the store. Since in the vast majority of cases the byte is in fact 0 because the card is already dirty this avoids doing unnecessary STRLB instructions. So it generates ldr rScratch, [xN] cbz rScratch, skip stlrb zr, [xN] skip: This, in combination with the previous patch generates significant performance improvements on programs that do extensive stores of non volatile oops. OK to push? Ed. Patch also available at http://people.linaro.org/~edward.nevill/patches/memorder.patch in case there is any problem with the formatting below. --- CUT HERE --- # HG changeset patch # User Edward Nevill edward.nevill@linaro.org # Date 1409322430 -3600 # Fri Aug 29 15:27:10 2014 +0100 # Node ID 953a1b5e5b1726470045bfa0dbe1b2bff799b906 # Parent 4aa306297dafb02943645761f2477d0d95c4a157 Optimise store of 0 byte into card table diff -r 4aa306297daf -r 953a1b5e5b17 src/cpu/aarch64/vm/aarch64.ad --- a/src/cpu/aarch64/vm/aarch64.ad Fri Aug 29 11:12:45 2014 +0100 +++ b/src/cpu/aarch64/vm/aarch64.ad Fri Aug 29 15:27:10 2014 +0100 @@ -2160,6 +2160,18 @@ rscratch1, stlrb); %} + // Special case of storing 0 to volatile for storing into card table + enc_class aarch64_enc_stlrb0(memory mem) %{ + Label skip; + { + MacroAssembler _masm(&cbuf); + __ ldrb(rscratch1, as_Register($mem$$base)); + __ cbz(rscratch1, skip); + } + MOV_VOLATILE(zr, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp, rscratch1, stlrb); + __ bind(skip); + %} + enc_class aarch64_enc_stlrh(iRegI src, memory mem) %{ MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp, rscratch1, stlrh); @@ -5909,6 +5921,19 @@ ins_pipe(pipe_class_memory); %} +// Special rule for store of 0 byte to volatile for card table +instruct storeB_volatile_imm0(immI0 zero, /* sync_memory*/indirect mem) +%{ + match(Set mem (StoreB mem zero)); + + ins_cost(VOLATILE_REF_COST); + format %{ "stlrb zr, $mem\t# byte" %} + + ins_encode(aarch64_enc_stlrb0(mem)); + + ins_pipe(pipe_class_memory); +%} + // Store Char/Short instruct storeC_volatile(iRegI src, /* sync_memory*/indirect mem) %{ diff -r 4aa306297daf -r 953a1b5e5b17 src/cpu/aarch64/vm/assembler_aarch64.hpp --- a/src/cpu/aarch64/vm/assembler_aarch64.hpp Fri Aug 29 11:12:45 2014 +0100 +++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp Fri Aug 29 15:27:10 2014 +0100 @@ -1081,7 +1081,7 @@ Register Rn, enum operand_size sz, int op, int o0) { starti; f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21); - rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0); + rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), zrf(Rt1, 0); } #define INSN4(NAME, sz, op, o0) /* Four registers */ \ --- CUT HERE ---