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[216.34.181.88]) by mx.google.com with ESMTPS id f5si703782icj.65.2014.08.25.12.20.33 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 25 Aug 2014 12:20:33 -0700 (PDT) Received-SPF: pass (google.com: domain of edk2-devel-bounces@lists.sourceforge.net designates 216.34.181.88 as permitted sender) client-ip=216.34.181.88; Received: from localhost ([127.0.0.1] helo=sfs-ml-3.v29.ch3.sourceforge.com) by sfs-ml-3.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1XLzoV-0000OX-Qv; Mon, 25 Aug 2014 19:20:23 +0000 Received: from sog-mx-4.v43.ch3.sourceforge.com ([172.29.43.194] helo=mx.sourceforge.net) by sfs-ml-3.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1XLzoT-0000OM-Uc for edk2-devel@lists.sourceforge.net; Mon, 25 Aug 2014 19:20:22 +0000 Received-SPF: pass (sog-mx-4.v43.ch3.sourceforge.com: domain of linaro.org designates 209.85.212.177 as permitted sender) client-ip=209.85.212.177; envelope-from=ard.biesheuvel@linaro.org; helo=mail-wi0-f177.google.com; Received: from mail-wi0-f177.google.com ([209.85.212.177]) by sog-mx-4.v43.ch3.sourceforge.com with esmtps (TLSv1:RC4-SHA:128) (Exim 4.76) id 1XLzoS-0003Wx-Oo for edk2-devel@lists.sourceforge.net; Mon, 25 Aug 2014 19:20:21 +0000 Received: by mail-wi0-f177.google.com with SMTP id ho1so3039615wib.16 for ; Mon, 25 Aug 2014 12:20:14 -0700 (PDT) X-Received: by 10.180.14.170 with SMTP id q10mr17236765wic.56.1408994414536; Mon, 25 Aug 2014 12:20:14 -0700 (PDT) Received: from ards-macbook-pro.local ([193.77.13.198]) by mx.google.com with ESMTPSA id b3sm3476891wiw.22.2014.08.25.12.20.07 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 25 Aug 2014 12:20:13 -0700 (PDT) From: Ard Biesheuvel To: lersek@redhat.com, olivier.martin@arm.com, edk2-devel@lists.sourceforge.net, peter.maydell@linaro.org, christoffer.dall@linaro.org, drjones@redhat.com, ilias.biris@linaro.org, leif.lindholm@linaro.org Date: Mon, 25 Aug 2014 21:19:22 +0200 Message-Id: <1408994367-11143-6-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1408994367-11143-1-git-send-email-ard.biesheuvel@linaro.org> References: <1408994367-11143-1-git-send-email-ard.biesheuvel@linaro.org> X-Spam-Score: -1.5 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record X-Headers-End: 1XLzoS-0003Wx-Oo Subject: [edk2] [PATCH 05/10] ArmPkg: allow dynamic GIC base addresses X-BeenThere: edk2-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list Reply-To: edk2-devel@lists.sourceforge.net List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.sourceforge.net X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Allow the PCDs gArmTokenSpaceGuid.PcdGicDistributorBase and gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase to be redeclared as PcdsDynamic by the platform, so virtual machines can set these properties during boot. As the PcdGet32() calls now call into the PCD database, cache the values that are required during the handling of interrupts. Signed-off-by: Ard Biesheuvel --- ArmPkg/ArmPkg.dec | 15 ++++++++------- ArmPkg/Drivers/ArmGic/ArmGicDxe.c | 34 ++++++++++++++++++++-------------- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf | 4 +++- ArmPkg/Library/BdsLib/BdsLib.inf | 2 +- 4 files changed, 32 insertions(+), 23 deletions(-) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 9229c07df53c..b654e7ca4552 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -68,6 +68,14 @@ # Define if the Power State Coordination Interface (PSCI) is supported by the Platform Trusted Firmware gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE|BOOLEAN|0x00000033 +[PcdsDynamic.common,PcdsFixedAtBuild.common] + # + # ARM Generic Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D + gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025 + [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006 @@ -81,13 +89,6 @@ gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005 # - # ARM Generic Interrupt Controller - # - gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D - gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025 - - # # ARM Secure Firmware PCDs # gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015 diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.c b/ArmPkg/Drivers/ArmGic/ArmGicDxe.c index 111ce144385b..42079f9e1f3a 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.c @@ -47,6 +47,9 @@ extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol; // EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL; +UINTN mGicInterruptInterfaceBase = 0; +UINTN mGicDistributorBase = 0; + // Maximum Number of Interrupts UINTN mGicNumInterrupts = 0; @@ -124,7 +127,7 @@ EnableInterruptSource ( RegShift = Source % 32; // Write set-enable register - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift); + MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift); return EFI_SUCCESS; } @@ -159,7 +162,7 @@ DisableInterruptSource ( RegShift = Source % 32; // Write set-enable register - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift); + MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift); return EFI_SUCCESS; } @@ -195,7 +198,7 @@ GetInterruptSourceState ( RegOffset = Source / 32; RegShift = Source % 32; - if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<= mGicNumInterrupts) { @@ -315,11 +318,11 @@ ExitBootServicesEvent ( } // Disable Gic Interface - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0); - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0); + MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0); + MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0); // Disable Gic Distributor - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0); + MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDDCR, 0x0); } /** @@ -349,7 +352,10 @@ InterruptDxeInitialize ( // Make sure the Interrupt Controller Protocol is not already installed in the system. ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid); - mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase)); + mGicInterruptInterfaceBase = PcdGet32(PcdGicInterruptInterfaceBase); + mGicDistributorBase = PcdGet32(PcdGicDistributorBase); + mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase); + ASSERT(mGicNumInterrupts < 4096); for (Index = 0; Index < mGicNumInterrupts; Index++) { DisableInterruptSource (&gHardwareInterruptProtocol, Index); @@ -358,7 +364,7 @@ InterruptDxeInitialize ( RegOffset = Index / 4; RegShift = (Index % 4) * 8; MmioAndThenOr32 ( - PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset), + mGicDistributorBase + ARM_GIC_ICDIPR + (4*RegOffset), ~(0xff << RegShift), ARM_GIC_DEFAULT_PRIORITY << RegShift ); @@ -387,16 +393,16 @@ InterruptDxeInitialize ( } // Set binary point reg to 0x7 (no preemption) - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7); + MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7); // Set priority mask reg to 0xff to allow all priorities through - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff); + MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff); // Enable gic cpu interface - MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1); + MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1); // Enable gic distributor - MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1); + MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDDCR, 0x1); // Initialize the array for the Interrupt Handlers gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts); diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf index 9dc557a03729..0ccd9935bc9e 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf @@ -41,15 +41,17 @@ MemoryAllocationLib UefiDriverEntryPoint IoLib + PcdLib [Protocols] gHardwareInterruptProtocolGuid gEfiCpuArchProtocolGuid -[FixedPcd.common] +[Pcd] gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase +[FixedPcd] gArmTokenSpaceGuid.PcdArmPrimaryCore [Depex] diff --git a/ArmPkg/Library/BdsLib/BdsLib.inf b/ArmPkg/Library/BdsLib/BdsLib.inf index 6158fba5919a..ce9300d00efc 100644 --- a/ArmPkg/Library/BdsLib/BdsLib.inf +++ b/ArmPkg/Library/BdsLib/BdsLib.inf @@ -91,7 +91,7 @@ [FixedPcd.ARM] gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset -[FixedPcd.AARCH64] +[Pcd.AARCH64] gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicSgiIntId