From patchwork Fri Aug 8 17:13:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 35152 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f72.google.com (mail-pa0-f72.google.com [209.85.220.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1902F2118A for ; Fri, 8 Aug 2014 17:16:32 +0000 (UTC) Received: by mail-pa0-f72.google.com with SMTP id eu11sf37797227pac.7 for ; Fri, 08 Aug 2014 10:16:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-post:list-help:list-subscribe:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:list-archive:content-type:content-transfer-encoding; bh=//0XvDdOprclXiEI0Rj0ojrfMcxHvkuouL+fyMkS3LY=; b=Zk5nNey7yW5qZ6BPMIRh426x0rbZYDXreTcOXFWDbOzVYTuVt2959eGDZDde+cks/g BNfNFQ0SGYXslTelazqiDCaedF6oVeDa7hUjDJQrVErYOmRDjpdCr5fcL8L/7vfcgpal fEi0qqhdO0mJCZ/Fu3ZFe19hEBOe0e5GWVgTIwRE8awiHnNGPOkBqIldl3bOGA2HT5/p jR+Z16sdV4CYQMDGPv1iqCwm2m6MSe4912sNOu4krKrrfIwjcLD8pSZ4DXaH/yJ82Eyo gUp9C2ceJEzoy1ANbUQ4nxpeLnAQBYRjHg7CCJBUP++YmOZs2moiK5fqQ9stkPmCYbhh eI/w== X-Gm-Message-State: ALoCoQkpqt8T8DblTqJe9ZktVP8zpaXWyQ2PW9wv6ynx2NC1ExfESG1ll2Y0i/U+4bwBLBMH0N15 X-Received: by 10.67.3.225 with SMTP id bz1mr13640185pad.16.1407518191421; Fri, 08 Aug 2014 10:16:31 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.87.214 with SMTP id r80ls632657qgd.44.gmail; Fri, 08 Aug 2014 10:16:31 -0700 (PDT) X-Received: by 10.52.129.200 with SMTP id ny8mr7656801vdb.27.1407518191302; Fri, 08 Aug 2014 10:16:31 -0700 (PDT) Received: from mail-vc0-f172.google.com (mail-vc0-f172.google.com [209.85.220.172]) by mx.google.com with ESMTPS id u7si3097349ves.73.2014.08.08.10.16.31 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 08 Aug 2014 10:16:31 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) client-ip=209.85.220.172; Received: by mail-vc0-f172.google.com with SMTP id im17so8810778vcb.3 for ; Fri, 08 Aug 2014 10:16:31 -0700 (PDT) X-Received: by 10.52.144.14 with SMTP id si14mr31693vdb.95.1407518191214; Fri, 08 Aug 2014 10:16:31 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp140446vcb; Fri, 8 Aug 2014 10:16:30 -0700 (PDT) X-Received: by 10.42.49.196 with SMTP id x4mr5059008icf.85.1407518189311; Fri, 08 Aug 2014 10:16:29 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id i7si4811159igm.42.2014.08.08.10.16.28 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 08 Aug 2014 10:16:29 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XFnlB-0000o3-FO; Fri, 08 Aug 2014 17:15:21 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XFnl8-0000m7-TQ for xen-devel@lists.xensource.com; Fri, 08 Aug 2014 17:15:19 +0000 Received: from [85.158.143.35:56154] by server-3.bemta-4.messagelabs.com id 9C/B5-06192-5A505E35; Fri, 08 Aug 2014 17:15:17 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-9.tower-21.messagelabs.com!1407518114!11976621!3 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.12.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22780 invoked from network); 8 Aug 2014 17:15:17 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-9.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 8 Aug 2014 17:15:17 -0000 X-IronPort-AV: E=Sophos;i="5.01,826,1400025600"; d="scan'208";a="160117697" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Fri, 8 Aug 2014 13:15:13 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1XFnky-0001op-Jn; Fri, 08 Aug 2014 18:15:08 +0100 From: Stefano Stabellini To: Date: Fri, 8 Aug 2014 18:13:53 +0100 Message-ID: <1407518033-10694-10-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v11 10/10] xen/arm: make accesses to desc->status flags atomic X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: This way we don't need to take the desc->lock in order to access desc->status in many of the gic and vgic functions. Using *_bit manipulation functions on desc->status is safe on arm64: status is an unsigned int but is the first field of a struct that contains pointers, therefore the alignement of the struct is at least 8 bytes. Signed-off-by: Stefano Stabellini Acked-by: Ian Campbell Acked-by: Julien Grall --- Changes in v10: - add in-code comment; - fix _IRQF_SHARED renaming. Changes in v2: - rebase on ab78724fc5628318b172b4344f7280621a151e1b. --- xen/arch/arm/gic-v2.c | 4 ++-- xen/arch/arm/gic.c | 6 +++--- xen/arch/arm/irq.c | 33 +++++++++++++++++---------------- xen/include/xen/irq.h | 5 +++++ 4 files changed, 27 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index da60a41..78ad4de 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -516,7 +516,7 @@ static void gicv2_irq_enable(struct irq_desc *desc) ASSERT(spin_is_locked(&desc->lock)); spin_lock_irqsave(&gicv2.lock, flags); - desc->status &= ~IRQ_DISABLED; + clear_bit(_IRQ_DISABLED, &desc->status); dsb(sy); /* Enable routing */ writel_gicd((1u << (irq % 32)), GICD_ISENABLER + (irq / 32) * 4); @@ -533,7 +533,7 @@ static void gicv2_irq_disable(struct irq_desc *desc) spin_lock_irqsave(&gicv2.lock, flags); /* Disable routing */ writel_gicd(1u << (irq % 32), GICD_ICENABLER + (irq / 32) * 4); - desc->status |= IRQ_DISABLED; + set_bit(_IRQ_DISABLED, &desc->status); spin_unlock_irqrestore(&gicv2.lock, flags); } diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 2aa9500..6611ba0 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -115,7 +115,7 @@ void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, { ASSERT(priority <= 0xff); /* Only 8 bits of priority */ ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that don't exist */ - ASSERT(desc->status & IRQ_DISABLED); + ASSERT(test_bit(_IRQ_DISABLED, &desc->status)); ASSERT(spin_is_locked(&desc->lock)); desc->handler = gic_hw_ops->gic_host_irq_type; @@ -133,7 +133,7 @@ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc, ASSERT(spin_is_locked(&desc->lock)); desc->handler = gic_hw_ops->gic_guest_irq_type; - desc->status |= IRQ_GUEST; + set_bit(_IRQ_GUEST, &desc->status); gic_set_irq_properties(desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ); @@ -369,7 +369,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) if ( p->desc != NULL ) { - p->desc->status &= ~IRQ_INPROGRESS; + clear_bit(_IRQ_INPROGRESS, &p->desc->status); if ( platform_has_quirk(PLATFORM_QUIRK_GUEST_PIRQ_NEED_EOI) ) gic_hw_ops->deactivate_irq(p->desc); } diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 7150c7a..25ecf1d 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -126,7 +126,7 @@ static inline struct domain *irq_get_domain(struct irq_desc *desc) { ASSERT(spin_is_locked(&desc->lock)); - if ( !(desc->status & IRQ_GUEST) ) + if ( !test_bit(_IRQ_GUEST, &desc->status) ) return dom_xen; ASSERT(desc->action != NULL); @@ -195,13 +195,13 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) goto out; } - if ( desc->status & IRQ_GUEST ) + if ( test_bit(_IRQ_GUEST, &desc->status) ) { struct domain *d = irq_get_domain(desc); desc->handler->end(desc); - desc->status |= IRQ_INPROGRESS; + set_bit(_IRQ_INPROGRESS, &desc->status); desc->arch.eoi_cpu = smp_processor_id(); /* the irq cannot be a PPI, we only support delivery of SPIs to @@ -210,22 +210,23 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) goto out_no_end; } - desc->status |= IRQ_PENDING; + set_bit(_IRQ_PENDING, &desc->status); /* * Since we set PENDING, if another processor is handling a different * instance of this same irq, the other processor will take care of it. */ - if ( desc->status & (IRQ_DISABLED | IRQ_INPROGRESS) ) + if ( test_bit(_IRQ_DISABLED, &desc->status) || + test_bit(_IRQ_INPROGRESS, &desc->status) ) goto out; - desc->status |= IRQ_INPROGRESS; + set_bit(_IRQ_INPROGRESS, &desc->status); - while ( desc->status & IRQ_PENDING ) + while ( test_bit(_IRQ_PENDING, &desc->status) ) { struct irqaction *action; - desc->status &= ~IRQ_PENDING; + clear_bit(_IRQ_PENDING, &desc->status); action = desc->action; spin_unlock_irq(&desc->lock); @@ -239,7 +240,7 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) spin_lock_irq(&desc->lock); } - desc->status &= ~IRQ_INPROGRESS; + clear_bit(_IRQ_INPROGRESS, &desc->status); out: desc->handler->end(desc); @@ -282,13 +283,13 @@ void release_irq(unsigned int irq, const void *dev_id) if ( !desc->action ) { desc->handler->shutdown(desc); - desc->status &= ~IRQ_GUEST; + clear_bit(_IRQ_GUEST, &desc->status); } spin_unlock_irqrestore(&desc->lock,flags); /* Wait to make sure it's not being used on another CPU */ - do { smp_mb(); } while ( desc->status & IRQ_INPROGRESS ); + do { smp_mb(); } while ( test_bit(_IRQ_INPROGRESS, &desc->status) ); if ( action->free_on_release ) xfree(action); @@ -305,13 +306,13 @@ static int __setup_irq(struct irq_desc *desc, unsigned int irqflags, * - if the IRQ is marked as shared * - dev_id is not NULL when IRQF_SHARED is set */ - if ( desc->action != NULL && (!(desc->status & IRQF_SHARED) || !shared) ) + if ( desc->action != NULL && (!test_bit(_IRQF_SHARED, &desc->status) || !shared) ) return -EINVAL; if ( shared && new->dev_id == NULL ) return -EINVAL; if ( shared ) - desc->status |= IRQF_SHARED; + set_bit(_IRQF_SHARED, &desc->status); new->next = desc->action; dsb(ish); @@ -332,7 +333,7 @@ int setup_irq(unsigned int irq, unsigned int irqflags, struct irqaction *new) spin_lock_irqsave(&desc->lock, flags); - if ( desc->status & IRQ_GUEST ) + if ( test_bit(_IRQ_GUEST, &desc->status) ) { struct domain *d = irq_get_domain(desc); @@ -396,10 +397,10 @@ int route_irq_to_guest(struct domain *d, unsigned int irq, { struct domain *ad = irq_get_domain(desc); - if ( (desc->status & IRQ_GUEST) && d == ad ) + if ( test_bit(_IRQ_GUEST, &desc->status) && d == ad ) goto out; - if ( desc->status & IRQ_GUEST ) + if ( test_bit(_IRQ_GUEST, &desc->status) ) printk(XENLOG_ERR "ERROR: IRQ %u is already used by domain %u\n", irq, ad->domain_id); else diff --git a/xen/include/xen/irq.h b/xen/include/xen/irq.h index 96d818f..ffb5932 100644 --- a/xen/include/xen/irq.h +++ b/xen/include/xen/irq.h @@ -76,6 +76,11 @@ struct msi_desc; * This is the "IRQ descriptor", which contains various information * about the irq, including what kind of hardware handling it has, * whether it is disabled etc etc. + * + * Note: on ARMv8 we can use normal bit manipulation functions to access + * the status field because struct irq_desc contains pointers, therefore + * the alignment of the struct is at least 8 bytes and status is the + * first field. */ typedef struct irq_desc { unsigned int status; /* IRQ status */