From patchwork Mon Jul 7 15:34:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edward Nevill X-Patchwork-Id: 33165 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f197.google.com (mail-pd0-f197.google.com [209.85.192.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 8C5C020969 for ; Mon, 7 Jul 2014 15:34:20 +0000 (UTC) Received: by mail-pd0-f197.google.com with SMTP id fp1sf31013975pdb.4 for ; Mon, 07 Jul 2014 08:34:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:message-id:subject:from:reply-to:to :cc:date:organization:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe:content-type :content-transfer-encoding; bh=7VQ64jZiQYuAT0XKbrnzn63IoWJvSw8Ovfc6BMhwFPk=; b=GCBZMdaF9fGUWJ8x7jT1kBD37nMXI4QiwHFf/IS4r31645JbwvwdIi5tsPvdwgfLld yYMutuz5KR8gYXaBPWOlH5AE7B9CzASigQE6xv5pQSgRh6hogZjGMH449nf29bgac32A UOHP5758tIhRqpYrFJZ/J84OlV17M7DUoff0OABp+PHS/dayNQt6RBnxi0IpfoUnHvWu L1NYT/exF2F4760/r6On1EELoRmO9rvAlFUkBENy7fngeXQPu/fH33WfmVmo92d87w40 T0n0Yg7Cd9GHLAkDouDH0A9X61dwDxwhdpbtkMd1hUUp3G6CboIXbMxNFfB9jRMLG55E zY5w== X-Gm-Message-State: ALoCoQlD/BdvMaTEmFzMIRDXEPW1IkRjaktX2UUDsuVjsKyzwDCSaQD5idma7RiIyzC6pZAJhZ2w X-Received: by 10.70.135.129 with SMTP id ps1mr13744916pdb.8.1404747259686; Mon, 07 Jul 2014 08:34:19 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.50.77 with SMTP id r71ls513044qga.71.gmail; Mon, 07 Jul 2014 08:34:19 -0700 (PDT) X-Received: by 10.58.197.193 with SMTP id iw1mr1323707vec.57.1404747259578; Mon, 07 Jul 2014 08:34:19 -0700 (PDT) Received: from mail-vc0-f170.google.com (mail-vc0-f170.google.com [209.85.220.170]) by mx.google.com with ESMTPS id d9si9736219vek.22.2014.07.07.08.34.19 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 07 Jul 2014 08:34:19 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) client-ip=209.85.220.170; Received: by mail-vc0-f170.google.com with SMTP id hy10so4164805vcb.1 for ; Mon, 07 Jul 2014 08:34:19 -0700 (PDT) X-Received: by 10.58.65.40 with SMTP id u8mr2358239ves.53.1404747259274; Mon, 07 Jul 2014 08:34:19 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp678246vcb; Mon, 7 Jul 2014 08:34:18 -0700 (PDT) X-Received: by 10.180.87.161 with SMTP id az1mr38701205wib.63.1404747258315; Mon, 07 Jul 2014 08:34:18 -0700 (PDT) Received: from mail-we0-f179.google.com (mail-we0-f179.google.com [74.125.82.179]) by mx.google.com with ESMTPS id bw4si41721527wib.64.2014.07.07.08.34.17 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 07 Jul 2014 08:34:18 -0700 (PDT) Received-SPF: pass (google.com: domain of edward.nevill@linaro.org designates 74.125.82.179 as permitted sender) client-ip=74.125.82.179; Received: by mail-we0-f179.google.com with SMTP id w62so4647673wes.10 for ; Mon, 07 Jul 2014 08:34:17 -0700 (PDT) X-Received: by 10.180.36.18 with SMTP id m18mr1778811wij.74.1404747257687; Mon, 07 Jul 2014 08:34:17 -0700 (PDT) Received: from [10.0.7.5] ([88.98.47.97]) by mx.google.com with ESMTPSA id q11sm116344734wib.14.2014.07.07.08.34.16 for (version=SSLv3 cipher=RC4-SHA bits=128/128); Mon, 07 Jul 2014 08:34:16 -0700 (PDT) Message-ID: <1404747253.4274.21.camel@localhost.localdomain> Subject: RFR: Optimised multiplyExact patch From: Edward Nevill Reply-To: edward.nevill@linaro.org To: "aarch64-port-dev@openjdk.java.net" Cc: patches@linaro.org Date: Mon, 07 Jul 2014 16:34:13 +0100 Organization: Linaro X-Mailer: Evolution 3.8.5 (3.8.5-2.fc19) Mime-Version: 1.0 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: edward.nevill@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Hi, The following patch optimises multiplyExact to generate the following code Integer case:- 0x0000007f751404e0: smull x8, w19, w11 0x0000007f751404e4: cmp x8, w8, sxtw 0x0000007f751404e8: b.ne 0x0000007f75140530 ;*invokestatic multiplyExact Long case:- 0x0000007f811404e0: mul x8, x19, x10 0x0000007f811404e4: smulh x9, x19, x10 0x0000007f811404e8: cmp x9, x8, asr #31 0x0000007f811404ec: b.ne 0x0000007f81140534 ;*invokestatic multiplyExact The patch has additional rules to convert the bvs after the multiply exact into a bne and therefor no longer needs the ugly code to generate the V flag from the Z flag. OK? Ed. --- CUT HERE --- # HG changeset patch # User Edward Nevill edward.nevill@linaro.org # Date 1404746752 -3600 # Mon Jul 07 16:25:52 2014 +0100 # Node ID 76a6867e8c34fb6ac892db0a0d2ea76aaf0c3415 # Parent aafb8a6d2b38862426dda0d3eb8061d7a1291fe0 Add support for multiplyExact diff -r aafb8a6d2b38 -r 76a6867e8c34 src/cpu/aarch64/vm/aarch64.ad --- a/src/cpu/aarch64/vm/aarch64.ad Mon Jul 07 16:24:51 2014 +0100 +++ b/src/cpu/aarch64/vm/aarch64.ad Mon Jul 07 16:25:52 2014 +0100 @@ -10602,6 +10602,96 @@ ins_pipe(pipe_class_default); %} +instruct overflowMulI_reg(rFlagsReg cr, iRegI op1, iRegI op2) +%{ + match(Set cr (OverflowMulI op1 op2)); + + format %{ "smull rscratch1, $op1, $op2\t# overflow check int\n\t" + "cmp rscratch1, rscratch1, sxtw\n\t" + "movw rscratch1, #0x80000000\n\t" + "cselw rscratch1, rscratch1, zr, NE\n\t" + "cmpw rscratch1, #1" %} + ins_cost(5 * INSN_COST); + ins_encode %{ + __ smull(rscratch1, $op1$$Register, $op2$$Register); + __ subs(zr, rscratch1, rscratch1, ext::sxtw); // NE => overflow + __ movw(rscratch1, 0x80000000); // Develop 0 (EQ), + __ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE) + __ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS + %} + + ins_pipe(pipe_class_default); +%} + +instruct overflowMulI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, rFlagsReg cr) +%{ + match(If cmp (OverflowMulI op1 op2)); + predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow + || n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow); + effect(USE labl, KILL cr); + + format %{ "smull rscratch1, $op1, $op2\t# overflow check int\n\t" + "cmp rscratch1, rscratch1, sxtw\n\t" + "b$cmp $labl" %} + ins_cost(3 * INSN_COST); // Branch is rare so treat as INSN_COST + ins_encode %{ + Label* L = $labl$$label; + Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode; + __ smull(rscratch1, $op1$$Register, $op2$$Register); + __ subs(zr, rscratch1, rscratch1, ext::sxtw); // NE => overflow + __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L); + %} + + ins_pipe(pipe_class_default); +%} + +instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2) +%{ + match(Set cr (OverflowMulL op1 op2)); + + format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t" + "smulh rscratch2, $op1, $op2\n\t" + "cmp rscratch2, rscratch1, ASR #31\n\t" + "movw rscratch1, #0x80000000\n\t" + "cselw rscratch1, rscratch1, zr, NE\n\t" + "cmpw rscratch1, #1" %} + ins_cost(6 * INSN_COST); + ins_encode %{ + __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63 + __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127 + __ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext + __ movw(rscratch1, 0x80000000); // Develop 0 (EQ), + __ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE) + __ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS + %} + + ins_pipe(pipe_class_default); +%} + +instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rFlagsReg cr) +%{ + match(If cmp (OverflowMulL op1 op2)); + predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow + || n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow); + effect(USE labl, KILL cr); + + format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t" + "smulh rscratch2, $op1, $op2\n\t" + "cmp rscratch2, rscratch1, ASR #31\n\t" + "b$cmp $labl" %} + ins_cost(4 * INSN_COST); // Branch is rare so treat as INSN_COST + ins_encode %{ + Label* L = $labl$$label; + Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode; + __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63 + __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127 + __ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext + __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L); + %} + + ins_pipe(pipe_class_default); +%} + // ============================================================================ // Compare Instructions --- CUT HERE ---