From patchwork Fri May 9 13:51:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edward Nevill X-Patchwork-Id: 29907 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f199.google.com (mail-pd0-f199.google.com [209.85.192.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id CFBD520534 for ; Fri, 9 May 2014 13:51:28 +0000 (UTC) Received: by mail-pd0-f199.google.com with SMTP id r10sf15845502pdi.10 for ; Fri, 09 May 2014 06:51:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:message-id:subject:from:reply-to:to :cc:date:organization:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe:content-type :content-transfer-encoding; bh=uuTZxZy6QnBAmGW4hpKT4y2PVOSEqLQGr0L3afJ64Jc=; b=itBz4FUaKDV2o13UzUhPr4KnSW1QjHph7kIJjNDuWR1sLD2Yes8A+8FR0KxG3vw7/4 MLT6BOw6Alch/hiZpOt6gFuUcMrwDZ/uP86NZu9eKJZsWDzVIJfSI97Od8A/r4w9oLnN hTMjg03gxcQhJhcJryOItEk7XGoOPeuMq5ZHB1e4BzbZ1mVLxXtUgJOWTyvfZmIN1qZq 3uMXhHnIPsFDc0zV4/o2P5Mt9zb+yOb9PpeS2ALg/D2FtmOKITAbwDn7ukMuxp6a+dNU h+LSHW4wdTYsV09BqBMped8SCXe49XKQ+XP64w5Doq0DcGlcZG3cXxFNwI13srXPzpLC l6dw== X-Gm-Message-State: ALoCoQlDuZgN8FrfqxwaFivkcwYmO7J6NVFQUJN1jWl6UEK/nxl+toQZB3oFSZQyqGiVqkZoZph4 X-Received: by 10.66.66.109 with SMTP id e13mr2543667pat.1.1399643488115; Fri, 09 May 2014 06:51:28 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.27.38 with SMTP id 35ls327623qgw.77.gmail; Fri, 09 May 2014 06:51:28 -0700 (PDT) X-Received: by 10.220.116.136 with SMTP id m8mr282362vcq.77.1399643487996; Fri, 09 May 2014 06:51:27 -0700 (PDT) Received: from mail-vc0-f181.google.com (mail-vc0-f181.google.com [209.85.220.181]) by mx.google.com with ESMTPS id rz3si732635veb.187.2014.05.09.06.51.27 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 09 May 2014 06:51:27 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) client-ip=209.85.220.181; Received: by mail-vc0-f181.google.com with SMTP id ld13so4633078vcb.40 for ; Fri, 09 May 2014 06:51:27 -0700 (PDT) X-Received: by 10.58.38.40 with SMTP id d8mr570146vek.61.1399643487603; Fri, 09 May 2014 06:51:27 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp81703vcb; Fri, 9 May 2014 06:51:27 -0700 (PDT) X-Received: by 10.180.208.52 with SMTP id mb20mr3485836wic.34.1399643486706; Fri, 09 May 2014 06:51:26 -0700 (PDT) Received: from mail-wg0-f41.google.com (mail-wg0-f41.google.com [74.125.82.41]) by mx.google.com with ESMTPS id na9si1007753wic.120.2014.05.09.06.51.25 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 09 May 2014 06:51:26 -0700 (PDT) Received-SPF: pass (google.com: domain of edward.nevill@linaro.org designates 74.125.82.41 as permitted sender) client-ip=74.125.82.41; Received: by mail-wg0-f41.google.com with SMTP id z12so4011839wgg.12 for ; Fri, 09 May 2014 06:51:25 -0700 (PDT) X-Received: by 10.194.190.42 with SMTP id gn10mr8773917wjc.9.1399643485877; Fri, 09 May 2014 06:51:25 -0700 (PDT) Received: from [10.0.7.5] ([88.98.47.97]) by mx.google.com with ESMTPSA id u3sm5544854wjw.49.2014.05.09.06.51.24 for (version=SSLv3 cipher=RC4-SHA bits=128/128); Fri, 09 May 2014 06:51:25 -0700 (PDT) Message-ID: <1399643484.8672.11.camel@localhost.localdomain> Subject: RFR: Optimise C2 entry point verification From: Edward Nevill Reply-To: edward.nevill@linaro.org To: "aarch64-port-dev@openjdk.java.net" Cc: patches@linaro.org Date: Fri, 09 May 2014 14:51:24 +0100 Organization: Linaro X-Mailer: Evolution 3.8.5 (3.8.5-2.fc19) Mime-Version: 1.0 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: edward.nevill@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Hi, The following patch makes a small optimsation to the entry point verification for C2. The patch replaces 0x00007fc5c111ebe0: ldr wscratch1, [x1,#8] ; {no_reloc} 0x00007fc5c111ebe4: lsl xscratch1, xscratch1, #3 0x00007fc5c111ebe8: cmp xscratch2, xscratch1 0x00007fc5c111ebec: b.eq 0x00007fc5c111ebf4 0x00007fc5c111ebf0: b 0x00007fc5c10cdb20 ; {runtime_call} 0x00007fc5c111ebf4: nop 0x00007fc5c111ebf8: nop 0x00007fc5c111ebfc: nop [Verified Entry Point] ... with the following 0x00007f077111ebe0: ldr wscratch1, [x1,#8] ; {no_reloc} 0x00007f077111ebe4: cmp xscratch2, xscratch1, lsl #3 0x00007f077111ebe8: b.eq 0x00007f077111ebf0 0x00007f077111ebec: b 0x00007f07710cdb20 ; {runtime_call} [Verified Entry Point] ... Should we also change CodeEntryAlignment which is currently set to 32? I can see very little point in the code entry alignment being less than a cache line. OK? Ed. --- CUT HERE --- exporting patch: # HG changeset patch # User Edward Nevill edward.nevill@linaro.org # Date 1399642797 -3600 # Fri May 09 14:39:57 2014 +0100 # Node ID 1b7ea58b2cf7b5e2dcbdbdecd387abd8bfa30176 # Parent f67f9b1b52ae8b1778dacb49df641bb5b6e48da1 Optimise C2 entry point verification diff -r f67f9b1b52ae -r 1b7ea58b2cf7 src/cpu/aarch64/vm/aarch64.ad --- a/src/cpu/aarch64/vm/aarch64.ad Thu May 01 14:57:36 2014 +0100 +++ b/src/cpu/aarch64/vm/aarch64.ad Fri May 09 14:39:57 2014 +0100 @@ -1421,9 +1421,8 @@ MacroAssembler _masm(&cbuf); // no need to worry about 4-byte of br alignment on AArch64 - __ load_klass(rscratch1, j_rarg0); + __ cmp_klass(j_rarg0, rscratch2, rscratch1); Label skip; - __ cmp(rscratch2, rscratch1); // TODO // can we avoid this skip and still use a reloc? __ br(Assembler::EQ, skip); diff -r f67f9b1b52ae -r 1b7ea58b2cf7 src/cpu/aarch64/vm/macroAssembler_aarch64.cpp --- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Thu May 01 14:57:36 2014 +0100 +++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Fri May 09 14:39:57 2014 +0100 @@ -2076,6 +2076,20 @@ } } +void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) { + if (UseCompressedClassPointers) { + ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); + if (Universe::narrow_klass_base() == NULL) { + cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift()); + return; + } + decode_klass_not_null(tmp); + } else { + ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); + } + cmp(trial_klass, tmp); +} + void MacroAssembler::load_prototype_header(Register dst, Register src) { load_klass(dst, src); ldr(dst, Address(dst, Klass::prototype_header_offset())); diff -r f67f9b1b52ae -r 1b7ea58b2cf7 src/cpu/aarch64/vm/macroAssembler_aarch64.hpp --- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp Thu May 01 14:57:36 2014 +0100 +++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp Fri May 09 14:39:57 2014 +0100 @@ -703,6 +703,7 @@ // oop manipulations void load_klass(Register dst, Register src); void store_klass(Register dst, Register src); + void cmp_klass(Register oop, Register trial_klass, Register tmp); void load_heap_oop(Register dst, Address src); --- CUT HERE ---