From patchwork Thu Sep 26 11:09:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 20588 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f199.google.com (mail-vc0-f199.google.com [209.85.220.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 952D524687 for ; Thu, 26 Sep 2013 11:10:25 +0000 (UTC) Received: by mail-vc0-f199.google.com with SMTP id lf12sf809316vcb.10 for ; Thu, 26 Sep 2013 04:10:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=QS/2Yx6xVauFeinUMyKZhNjvwAIiKkfe68cFCQTC1FE=; b=fmIU6dK/qEs43wmH7z1nIvULDQT4GzySOv0Rf7gBXggzWCbbrVN3YJ6Svh6B599ZjT gwO1cGzRAsn4xZVNH7PmaToaFwRVnAFdFdO90ORWWPyaN5EPlrDrRScpke5/q3bfTiU/ ZKu+ycqT8WgeyZ3SLpOG4mTHCh5eIwU5OZDMNxUy0GFzYiU9a657rfdFp/UD4xefLQYG j1U9nmjgX/Q5DpOPDBSNzDik6SxNJ0Fhg546pZI5GLlYCwW6PpCr1+OaNz66LZe6EbeY Z1OmzvCizpKs+DuWkjCXs4QA0QAlDXzdfgT8QPx+TAAl9VM5QqoDPtGPdPqU+sLE3GRs G4pQ== X-Gm-Message-State: ALoCoQmxgOj6sLbPaec6MxkUhdShGiF0SCYxjIGkMw9HgBTEPi0L3ytTvM3kyHQ86/6ENEfEZ3rk X-Received: by 10.236.56.70 with SMTP id l46mr82662yhc.2.1380193825387; Thu, 26 Sep 2013 04:10:25 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.29.129 with SMTP id k1ls872395qeh.75.gmail; Thu, 26 Sep 2013 04:10:25 -0700 (PDT) X-Received: by 10.221.53.74 with SMTP id vp10mr151450vcb.54.1380193825295; Thu, 26 Sep 2013 04:10:25 -0700 (PDT) Received: from mail-vb0-f46.google.com (mail-vb0-f46.google.com [209.85.212.46]) by mx.google.com with ESMTPS id mj10si260537vcb.12.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 04:10:25 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.46 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.46; Received: by mail-vb0-f46.google.com with SMTP id p13so700977vbe.5 for ; Thu, 26 Sep 2013 04:09:55 -0700 (PDT) X-Received: by 10.220.84.65 with SMTP id i1mr106895vcl.51.1380193795178; Thu, 26 Sep 2013 04:09:55 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp359569vcz; Thu, 26 Sep 2013 04:09:54 -0700 (PDT) X-Received: by 10.194.175.66 with SMTP id by2mr248805wjc.59.1380193793966; Thu, 26 Sep 2013 04:09:53 -0700 (PDT) Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by mx.google.com with ESMTPS id jo9si399776wjc.114.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 04:09:53 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.177 is neither permitted nor denied by best guess record for domain of julien.grall@linaro.org) client-ip=209.85.212.177; Received: by mail-wi0-f177.google.com with SMTP id cb5so1022622wib.16 for ; Thu, 26 Sep 2013 04:09:53 -0700 (PDT) X-Received: by 10.180.20.163 with SMTP id o3mr27445351wie.1.1380193793510; Thu, 26 Sep 2013 04:09:53 -0700 (PDT) Received: from belegaer.uk.xensource.com. ([185.25.64.249]) by mx.google.com with ESMTPSA id q5sm2409641wiz.3.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 04:09:53 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: stefano.stabellini@eu.citrix.com, ian.campbell@citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH v5 4/7] xen/arm: gic: Use the correct CPU ID Date: Thu, 26 Sep 2013 12:09:38 +0100 Message-Id: <1380193781-17474-5-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1380193781-17474-1-git-send-email-julien.grall@linaro.org> References: <1380193781-17474-1-git-send-email-julien.grall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.46 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The GIC mapping of CPU interfaces does not necessarily match the logical CPU numbering. When Xen wants to send an SGI to specific CPU, it needs to use the GIC CPU ID. It can be retrieved from ITARGETSR0, in fact when this field is read, the GIC will return a value that corresponds only to the processor reading the register. So Xen can use the PPI 0 to initialize the mapping. Signed-off-by: Julien Grall --- Changes in v5: - Remove the per_cpu ASSERT. Changes in v4: - Make logical and between the cpumask given in arguments and cpu_possible_map. - Make sure the per_cpu is initialized - Add comment restriction for gic_set_irq_properties Changes in v3: - Correctly create the mask in gic_cpu_mask Changes in v2: - Use per-cpu variable instead of an array - Add comment for NR_GIC_CPU_IF --- xen/arch/arm/gic.c | 45 +++++++++++++++++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index b969d23..05685cd 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -57,6 +57,31 @@ static DEFINE_PER_CPU(uint64_t, lr_mask); static unsigned nr_lrs; +/* The GIC mapping of CPU interfaces does not necessarily match the + * logical CPU numbering. Let's use mapping as returned by the GIC + * itself + */ +static DEFINE_PER_CPU(u8, gic_cpu_id); + +/* Maximum cpu interface per GIC */ +#define NR_GIC_CPU_IF 8 + +static unsigned int gic_cpu_mask(const cpumask_t *cpumask) +{ + unsigned int cpu; + unsigned int mask = 0; + cpumask_t possible_mask; + + cpumask_and(&possible_mask, cpumask, &cpu_possible_map); + for_each_cpu(cpu, &possible_mask) + { + ASSERT(cpu < NR_GIC_CPU_IF); + mask |= per_cpu(gic_cpu_id, cpu); + } + + return mask; +} + unsigned int gic_number_lines(void) { return gic.lines; @@ -182,16 +207,18 @@ static hw_irq_controller gic_guest_irq_type = { .set_affinity = gic_irq_set_affinity, }; -/* needs to be called with gic.lock held */ +/* + * - needs to be called with gic.lock held + * - needs to be called with a valid cpu_mask, ie each cpu in the mask has + * already called gic_cpu_init + */ static void gic_set_irq_properties(unsigned int irq, bool_t level, const cpumask_t *cpu_mask, unsigned int priority) { volatile unsigned char *bytereg; uint32_t cfg, edgebit; - unsigned int mask = cpumask_bits(cpu_mask)[0]; - - ASSERT(!(mask & ~0xff)); /* Target bitmap only support 8 CPUS */ + unsigned int mask = gic_cpu_mask(cpu_mask); /* Set edge / level */ cfg = GICD[GICD_ICFGR + irq / 16]; @@ -300,6 +327,8 @@ static void __cpuinit gic_cpu_init(void) { int i; + this_cpu(gic_cpu_id) = GICD[GICD_ITARGETSR] & 0xff; + /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so * even though they are controlled with GICD registers, they must * be set up here with the other per-cpu state. */ @@ -431,13 +460,13 @@ void __init gic_init(void) void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi) { - unsigned long mask = cpumask_bits(cpumask)[0]; + unsigned int mask = 0; + cpumask_t online_mask; ASSERT(sgi < 16); /* There are only 16 SGIs */ - mask &= cpumask_bits(&cpu_online_map)[0]; - - ASSERT(mask < 0x100); /* The target bitmap only supports 8 CPUs */ + cpumask_and(&online_mask, cpumask, &cpu_online_map); + mask = gic_cpu_mask(&online_mask); dsb();