From patchwork Wed Sep 18 13:15:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 20437 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f72.google.com (mail-yh0-f72.google.com [209.85.213.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 650E426114 for ; Wed, 18 Sep 2013 13:15:36 +0000 (UTC) Received: by mail-yh0-f72.google.com with SMTP id z20sf7400092yhz.11 for ; Wed, 18 Sep 2013 06:15:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=dH5I38ycurG7lxlbk9sq3phtEzyNrrZG4q29NTrJCls=; b=iPbHEccCRSuFAXh+El7Q+z28n+tRILcn2mu5lK7BtRXUEX2fEtGeoLKHOgyF1uNjfx TbaNgI4EXmFtpP8VeLZssQhnVfys4VhM5A/cmskThY+jyOv0IlHsFBVYu1nuYaUwx7WB ZVpSy0+KbFf1ZeOfRpabxSgkupothfGqWSFToisKq20IJOBNDuqQKGeWohXjI+ToOjhr aXL1fBq6AYEGbzdU+/Wsrh/EzSX2eswUNW+oFqmVZUmtOtLBWLAxmPi2cIWVrwiYJI8l 849RoEAVQCWDDY1RWD9RSume68dtradK87fB5x70sk61L/eTr93amxTlaXnraxk8tCsb 0w/w== X-Gm-Message-State: ALoCoQnHYdBoc3hNZcL8wwf43rh9zRvfqZXvKIZvQnvn0jMlUieRAOSQBRWOthvLqQJxRS62B4Ma X-Received: by 10.236.69.35 with SMTP id m23mr14881622yhd.6.1379510136212; Wed, 18 Sep 2013 06:15:36 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.53.103 with SMTP id a7ls3309049qep.90.gmail; Wed, 18 Sep 2013 06:15:36 -0700 (PDT) X-Received: by 10.52.161.231 with SMTP id xv7mr5026665vdb.1.1379510135957; Wed, 18 Sep 2013 06:15:35 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id ee8si511580vdc.41.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Sep 2013 06:15:35 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id gd11so5113550vcb.19 for ; Wed, 18 Sep 2013 06:15:35 -0700 (PDT) X-Received: by 10.221.6.195 with SMTP id ol3mr203822vcb.34.1379510135866; Wed, 18 Sep 2013 06:15:35 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp217411vcz; Wed, 18 Sep 2013 06:15:35 -0700 (PDT) X-Received: by 10.15.34.135 with SMTP id e7mr3016087eev.63.1379510132224; Wed, 18 Sep 2013 06:15:32 -0700 (PDT) Received: from mail-ea0-f182.google.com (mail-ea0-f182.google.com [209.85.215.182]) by mx.google.com with ESMTPS id c49si1819918eeg.27.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Sep 2013 06:15:32 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.215.182 is neither permitted nor denied by best guess record for domain of julien.grall@linaro.org) client-ip=209.85.215.182; Received: by mail-ea0-f182.google.com with SMTP id o10so3428733eaj.41 for ; Wed, 18 Sep 2013 06:15:29 -0700 (PDT) X-Received: by 10.14.183.130 with SMTP id q2mr60102920eem.5.1379510129421; Wed, 18 Sep 2013 06:15:29 -0700 (PDT) Received: from belegaer.uk.xensource.com. ([185.25.64.249]) by mx.google.com with ESMTPSA id n48sm2689190eeg.17.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Sep 2013 06:15:29 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: stefano.stabellini@eu.citrix.com, ian.campbell@citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH v3 3/6] xen/arm: gic: Use the correct CPU ID Date: Wed, 18 Sep 2013 14:15:19 +0100 Message-Id: <1379510122-9467-4-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1379510122-9467-1-git-send-email-julien.grall@linaro.org> References: <1379510122-9467-1-git-send-email-julien.grall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The GIC mapping of CPU interfaces does not necessarily match the logical CPU numbering. When Xen wants to send an SGI to specific CPU, it needs to use the GIC CPU ID. It can be retrieved from ITARGETSR0, in fact when this field is read, the GIC will return a value that corresponds only to the processor reading the register. So Xen can use the PPI 0 to initialize the mapping. Signed-off-by: Julien Grall --- Changes in v3: - Correctly create the mask in gic_cpu_mask Changes in v2: - Use per-cpu variable instead of an array - Add comment for NR_GIC_CPU_IF --- xen/arch/arm/gic.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index b969d23..4061691 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -57,6 +57,29 @@ static DEFINE_PER_CPU(uint64_t, lr_mask); static unsigned nr_lrs; +/* The GIC mapping of CPU interfaces does not necessarily match the + * logical CPU numbering. Let's use mapping as returned by the GIC + * itself + */ +static DEFINE_PER_CPU(u8, gic_cpu_id); + +/* Maximum cpu interface per GIC */ +#define NR_GIC_CPU_IF 8 + +static unsigned int gic_cpu_mask(const cpumask_t *cpumask) +{ + unsigned int cpu; + unsigned int mask = 0; + + for_each_cpu(cpu, cpumask) + { + ASSERT(cpu < NR_GIC_CPU_IF); + mask |= per_cpu(gic_cpu_id, cpu); + } + + return mask; +} + unsigned int gic_number_lines(void) { return gic.lines; @@ -189,9 +212,7 @@ static void gic_set_irq_properties(unsigned int irq, bool_t level, { volatile unsigned char *bytereg; uint32_t cfg, edgebit; - unsigned int mask = cpumask_bits(cpu_mask)[0]; - - ASSERT(!(mask & ~0xff)); /* Target bitmap only support 8 CPUS */ + unsigned int mask = gic_cpu_mask(cpu_mask); /* Set edge / level */ cfg = GICD[GICD_ICFGR + irq / 16]; @@ -300,6 +321,8 @@ static void __cpuinit gic_cpu_init(void) { int i; + this_cpu(gic_cpu_id) = GICD[GICD_ITARGETSR] & 0xff; + /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so * even though they are controlled with GICD registers, they must * be set up here with the other per-cpu state. */ @@ -431,13 +454,13 @@ void __init gic_init(void) void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi) { - unsigned long mask = cpumask_bits(cpumask)[0]; + cpumask_t online_mask; + unsigned int mask = 0; ASSERT(sgi < 16); /* There are only 16 SGIs */ - mask &= cpumask_bits(&cpu_online_map)[0]; - - ASSERT(mask < 0x100); /* The target bitmap only supports 8 CPUs */ + cpumask_and(&online_mask, cpumask, &cpu_online_map); + mask = gic_cpu_mask(&online_mask); dsb();