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[188.246.204.87]) by mx.google.com with ESMTPSA id jf2sm24921667wic.2.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 27 Aug 2013 03:36:12 -0700 (PDT) From: Steve Capper To: linaro-dev Cc: steve.mcintyre@linaro.org, leif.lindholm@linaro.org, patches@linaro.org, Steve Capper Subject: [PATCH 2/2] ARM: Add IT instructions to inline assembler Date: Tue, 27 Aug 2013 11:36:00 +0100 Message-Id: <1377599760-5751-3-git-send-email-steve.capper@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1377599760-5751-1-git-send-email-steve.capper@linaro.org> References: <1377599760-5751-1-git-send-email-steve.capper@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: steve.capper@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.52 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Leif Lindholm External code that uses libTBB will pull in gcc_armv7.h, which has inline assembler that contains conditional instructions. Unfortunately these external programs won't necessarily have the `-Wa,-mimplicit-it=thumb' build option when compiling for Thumb state, thus may fail to build for Thumb under older build systems. To remedy this, we add the IT instructions to gcc_armv7.h that would normally be added implicitly by the assembler. Signed-off-by: Steve Capper --- include/tbb/machine/gcc_armv7.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/tbb/machine/gcc_armv7.h b/include/tbb/machine/gcc_armv7.h index fde1f7a..05ef6a9 100644 --- a/include/tbb/machine/gcc_armv7.h +++ b/include/tbb/machine/gcc_armv7.h @@ -88,6 +88,7 @@ static inline int32_t __TBB_machine_cmpswp4(volatile void *ptr, int32_t value, i "ldrex %1, [%3]\n" "mov %0, #0\n" "cmp %1, %4\n" + "it eq\n" "strexeq %0, %5, [%3]\n" : "=&r" (res), "=&r" (oldval), "+Qo" (*(volatile int32_t*)ptr) : "r" ((int32_t *)ptr), "Ir" (comparand), "r" (value) @@ -118,7 +119,9 @@ static inline int64_t __TBB_machine_cmpswp8(volatile void *ptr, int64_t value, i "mov %0, #0\n" "ldrexd %1, %H1, [%3]\n" "cmp %1, %4\n" + "it eq\n" "cmpeq %H1, %H4\n" + "it eq\n" "strexdeq %0, %5, %H5, [%3]" : "=&r" (res), "=&r" (oldval), "+Qo" (*(volatile int64_t*)ptr) : "r" ((int64_t *)ptr), "r" (comparand), "r" (value)