From patchwork Tue Aug 13 15:12:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 19091 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f71.google.com (mail-qa0-f71.google.com [209.85.216.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 8EF49246B8 for ; Tue, 13 Aug 2013 15:13:49 +0000 (UTC) Received: by mail-qa0-f71.google.com with SMTP id bq6sf4191918qab.10 for ; Tue, 13 Aug 2013 08:13:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=oALT2xRF4eepSTRe2h/xW3s0OfilhKbeA5g0kQT062w=; b=Ek8IFQupjRKbjp8B/nQ/M1chot/DkzrTSMxW4TNOEyX0jX4IwgX26ZK4CH12Ml0qJe V52AAP+vVuEwDx8hLhSjkWFAlx0BOnSiw8yIz5Hp3FxF6KSxyIrBMeeMDslu7tSjQei2 CJNlvQK8181i0NayUPnfOWQ5BhB5y4g4Mj0l5p0795xdMpO7cjU16ImyuU5J2nXbheGN OVYv3TPHO1BYPX8A7nO06XRiSSSSzLNxTRKZkUfKhhhskxesqf0eKylhitZIqp5W53zH mraBjKm+PF//UCKCLV/xY5+b7SNbnLNUhvfCPJUHu3lgl3GKd95MhZFWEZYReZxKDhlM XjLQ== X-Received: by 10.236.120.232 with SMTP id p68mr1813186yhh.43.1376406829018; Tue, 13 Aug 2013 08:13:49 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.47.11 with SMTP id z11ls2933174qem.68.gmail; Tue, 13 Aug 2013 08:13:48 -0700 (PDT) X-Received: by 10.220.162.135 with SMTP id v7mr1169011vcx.35.1376406828893; Tue, 13 Aug 2013 08:13:48 -0700 (PDT) Received: from mail-ve0-f170.google.com (mail-ve0-f170.google.com [209.85.128.170]) by mx.google.com with ESMTPS id o7si7466566vcl.60.2013.08.13.08.13.48 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 13 Aug 2013 08:13:48 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.170; Received: by mail-ve0-f170.google.com with SMTP id 15so6835838vea.29 for ; Tue, 13 Aug 2013 08:13:48 -0700 (PDT) X-Gm-Message-State: ALoCoQmLhjTt28Px9rX3Wc0MR0ax3UuISV7oomYWkdHGkc4V6sdHgcEwhchwf9x1Np2fFkFqIbCV X-Received: by 10.52.117.208 with SMTP id kg16mr996777vdb.48.1376406828670; Tue, 13 Aug 2013 08:13:48 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp159511vcz; Tue, 13 Aug 2013 08:13:48 -0700 (PDT) X-Received: by 10.60.142.231 with SMTP id rz7mr4790008oeb.44.1376406827968; Tue, 13 Aug 2013 08:13:47 -0700 (PDT) Received: from mail-oa0-f46.google.com (mail-oa0-f46.google.com [209.85.219.46]) by mx.google.com with ESMTPS id sb9si18993584obc.58.2013.08.13.08.13.47 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 13 Aug 2013 08:13:47 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.219.46 is neither permitted nor denied by best guess record for domain of andre.przywara@linaro.org) client-ip=209.85.219.46; Received: by mail-oa0-f46.google.com with SMTP id l10so11401765oag.5 for ; Tue, 13 Aug 2013 08:13:47 -0700 (PDT) X-Received: by 10.60.58.71 with SMTP id o7mr4886623oeq.51.1376406827518; Tue, 13 Aug 2013 08:13:47 -0700 (PDT) Received: from slackpad.drs.calxeda.com (g224199244.adsl.alicedsl.de. [92.224.199.244]) by mx.google.com with ESMTPSA id z5sm39413872obg.13.2013.08.13.08.13.45 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 13 Aug 2013 08:13:47 -0700 (PDT) From: Andre Przywara To: stefano.stabellini@eu.citrix.com, Ian.Campbell@citrix.com, julien.grall@linaro.org Cc: xen-devel@lists.xen.org, patches@linaro.org, Andre Przywara Subject: [PATCH] PL011: fix reverse logic for interrupt mask register Date: Tue, 13 Aug 2013 17:12:35 +0200 Message-Id: <1376406755-23703-1-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: andre.przywara@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The PL011 IMSC register description is somehow fuzzy in the documentation; by comparing it with the Linux implementation one can see that the logic is actually reversed to Xen's implementation: A "0" in field means interrupt disabled, a "1" enables it. Therefore we enabled all interrupts instead of disabling them in the beginning and later on masked the wrong interrupts. Unclear how this worked on the Versatile Express, but this fix is needed to get Calxeda Midway running (and works on VExpress, too). Signed-off-by: Andre Przywara --- xen/drivers/char/pl011.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 05d034f..8e90520 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -87,7 +87,7 @@ static void __init pl011_init_preirq(struct serial_port *port) unsigned int divisor; /* No interrupts, please. */ - pl011_write(uart, IMSC, ALLI); + pl011_write(uart, IMSC, 0); /* Definitely no DMA */ pl011_write(uart, DMACR, 0x0); @@ -115,7 +115,7 @@ static void __init pl011_init_preirq(struct serial_port *port) pl011_write(uart, RSR, 0); /* Mask and clear the interrupts */ - pl011_write(uart, IMSC, ALLI); + pl011_write(uart, IMSC, 0); pl011_write(uart, ICR, ALLI); /* Enable the UART for RX and TX; no flow ctrl */ @@ -140,7 +140,7 @@ static void __init pl011_init_postirq(struct serial_port *port) pl011_write(uart, ICR, OEI|BEI|PEI|FEI); /* Unmask interrupts */ - pl011_write(uart, IMSC, RTI|DSRMI|DCDMI|CTSMI|RIMI); + pl011_write(uart, IMSC, OEI|BEI|PEI|FEI|TXI|RXI); } static void pl011_suspend(struct serial_port *port)