From patchwork Wed Jul 31 15:38:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 18710 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f70.google.com (mail-qa0-f70.google.com [209.85.216.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4AEAB246CC for ; Wed, 31 Jul 2013 15:38:39 +0000 (UTC) Received: by mail-qa0-f70.google.com with SMTP id cd7sf1173178qab.5 for ; Wed, 31 Jul 2013 08:38:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-removed-original-auth :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:x-google-group-id:list-post:list-help :list-archive:list-unsubscribe; bh=fqx5jVyj+0gEDhX3JkMWVtlvfBQkfkx/qRPQ9qiZkH0=; b=K/GIiNYIdKMHdyCTqIc+BhZeUDHvJz0g3DzyEPiDFRXk0H/VDbUV9pXAajJLtBL7jo yXUFTjDU2pgcUjE6Y3uu5bP+FS3HGGsj4H55c9f9oxbbl/BhMLh3Z6cw3k2Mw2E9nqvk gw4j4Dc0KomEvjkLek3HUD2kVcgz0UF4qP6py44tSN6eIP1k1y0ltDx06SSTOJNxMb2P 8lliluufdyGOGASd0cflaYHIlPtbe6y/lNSkryPRl8G3n2DOXOGKScyAOH04ueJcWpAq 0/puUeJhn/cc0QqlqVdlbfiWac4IzE+E4mG9tFWkkdZWmJYLOUXneecuB3YUyX9ytPoS eaKA== X-Received: by 10.236.120.232 with SMTP id p68mr35073643yhh.43.1375285118949; Wed, 31 Jul 2013 08:38:38 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.106.134 with SMTP id gu6ls644451qeb.83.gmail; Wed, 31 Jul 2013 08:38:38 -0700 (PDT) X-Received: by 10.220.58.195 with SMTP id i3mr11793361vch.38.1375285118791; Wed, 31 Jul 2013 08:38:38 -0700 (PDT) Received: from mail-ve0-f175.google.com (mail-ve0-f175.google.com [209.85.128.175]) by mx.google.com with ESMTPS id fo4si422475vec.22.2013.07.31.08.38.38 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 31 Jul 2013 08:38:38 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.175; Received: by mail-ve0-f175.google.com with SMTP id oy10so943513veb.20 for ; Wed, 31 Jul 2013 08:38:38 -0700 (PDT) X-Received: by 10.52.164.16 with SMTP id ym16mr23840208vdb.32.1375285118667; Wed, 31 Jul 2013 08:38:38 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.11.8 with SMTP id pc8csp243355vcb; Wed, 31 Jul 2013 08:38:37 -0700 (PDT) X-Received: by 10.180.98.233 with SMTP id el9mr4667903wib.54.1375285117479; Wed, 31 Jul 2013 08:38:37 -0700 (PDT) Received: from mail-wg0-f45.google.com (mail-wg0-f45.google.com [74.125.82.45]) by mx.google.com with ESMTPS id nb9si13528019wic.85.2013.07.31.08.38.36 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 31 Jul 2013 08:38:37 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.45 is neither permitted nor denied by best guess record for domain of julien.grall@linaro.org) client-ip=74.125.82.45; Received: by mail-wg0-f45.google.com with SMTP id x12so749814wgg.12 for ; Wed, 31 Jul 2013 08:38:36 -0700 (PDT) X-Received: by 10.180.74.210 with SMTP id w18mr4744859wiv.20.1375285116698; Wed, 31 Jul 2013 08:38:36 -0700 (PDT) Received: from belegaer.uk.xensource.com. (firewall.ctxuk.citrix.com. [46.33.159.2]) by mx.google.com with ESMTPSA id u9sm3135483wif.6.2013.07.31.08.38.35 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 31 Jul 2013 08:38:35 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org, ian.campbell@citrix.com Cc: stefano.stabellini@eu.citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH v2 1/8] pl011: Use ioreadl/iowritel Date: Wed, 31 Jul 2013 16:38:21 +0100 Message-Id: <1375285109-3053-2-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1375285109-3053-1-git-send-email-julien.grall@linaro.org> References: <1375285109-3053-1-git-send-email-julien.grall@linaro.org> X-Gm-Message-State: ALoCoQmE4KXKILi/buusrMs3YW1z4/aM2LgXfwIp+bLLVB/+dZn5BeMzelDGsxw7yde7GF2meKtu X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Signed-off-by: Julien Grall Acked-by: Ian Campbell --- xen/drivers/char/pl011.c | 80 ++++++++++++++++++++++++---------------------- 1 file changed, 42 insertions(+), 38 deletions(-) diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 05b5ef1..9456f20 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -32,7 +32,7 @@ static struct pl011 { unsigned int baud, clock_hz, data_bits, parity, stop_bits; struct dt_irq irq; - volatile uint32_t *regs; + void __iomem *regs; /* UART with IRQ line: interrupt-driven I/O. */ struct irqaction irqaction; /* /\* UART with no IRQ line: periodically-polled I/O. *\/ */ @@ -42,20 +42,20 @@ static struct pl011 { } pl011_com = {0}; /* PL011 register addresses */ -#define DR (0x00/4) -#define RSR (0x04/4) -#define FR (0x18/4) -#define ILPR (0x20/4) -#define IBRD (0x24/4) -#define FBRD (0x28/4) -#define LCR_H (0x2c/4) -#define CR (0x30/4) -#define IFLS (0x34/4) -#define IMSC (0x38/4) -#define RIS (0x3c/4) -#define MIS (0x40/4) -#define ICR (0x44/4) -#define DMACR (0x48/4) +#define DR (0x00) +#define RSR (0x04) +#define FR (0x18) +#define ILPR (0x20) +#define IBRD (0x24) +#define FBRD (0x28) +#define LCR_H (0x2c) +#define CR (0x30) +#define IFLS (0x34) +#define IMSC (0x38) +#define RIS (0x3c) +#define MIS (0x40) +#define ICR (0x44) +#define DMACR (0x48) /* CR bits */ #define RXE (1<<9) /* Receive enable */ @@ -95,17 +95,20 @@ static struct pl011 { #define PARITY_MARK (PEN|SPS) #define PARITY_SPACE (PEN|EPS|SPS) +#define pl011_read(uart, off) ioreadl((uart)->regs + (off)) +#define pl011_write(uart, off,val) iowritel((uart)->regs + (off), (val)) + static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs) { struct serial_port *port = data; struct pl011 *uart = port->uart; - unsigned int status = uart->regs[MIS]; + unsigned int status = pl011_read(uart, MIS); if ( status ) { do { - uart->regs[ICR] = status & ~(TXI|RTI|RXI); + pl011_write(uart, ICR, status & ~(TXI|RTI|RXI)); if ( status & (RTI|RXI) ) serial_rx_interrupt(port, regs); @@ -118,7 +121,7 @@ static void pl011_interrupt(int irq, void *data, struct cpu_user_regs *regs) if ( status & (TXI) ) serial_tx_interrupt(port, regs); - status = uart->regs[MIS]; + status = pl011_read(uart, MIS); } while (status != 0); } } @@ -129,40 +132,39 @@ static void __init pl011_init_preirq(struct serial_port *port) unsigned int divisor; /* No interrupts, please. */ - uart->regs[IMSC] = ALLI; + pl011_write(uart, IMSC, ALLI); /* Definitely no DMA */ - uart->regs[DMACR] = 0x0; + pl011_write(uart, DMACR, 0x0); /* Line control and baud-rate generator. */ if ( uart->baud != BAUD_AUTO ) { /* Baud rate specified: program it into the divisor latch. */ divisor = (uart->clock_hz << 2) / uart->baud; /* clk << 6 / bd << 4 */ - uart->regs[FBRD] = divisor & 0x3f; - uart->regs[IBRD] = divisor >> 6; + pl011_write(uart, FBRD, divisor & 0x3f); + pl011_write(uart, IBRD, divisor >> 6); } else { /* Baud rate already set: read it out from the divisor latch. */ - divisor = (uart->regs[IBRD] << 6) | uart->regs[FBRD]; + divisor = (pl011_read(uart, IBRD) << 6) | (pl011_read(uart, FBRD)); uart->baud = (uart->clock_hz << 2) / divisor; } /* This write must follow FBRD and IBRD writes. */ - uart->regs[LCR_H] = ( (uart->data_bits - 5) << 5 - | FEN - | ((uart->stop_bits - 1) << 3) - | uart->parity ); - + pl011_write(uart, LCR_H, (uart->data_bits - 5) << 5 + | FEN + | ((uart->stop_bits - 1) << 3) + | uart->parity); /* Clear errors */ - uart->regs[RSR] = 0; + pl011_write(uart, RSR, 0); /* Mask and clear the interrupts */ - uart->regs[IMSC] = ALLI; - uart->regs[ICR] = ALLI; + pl011_write(uart, IMSC, ALLI); + pl011_write(uart, ICR, ALLI); /* Enable the UART for RX and TX; no flow ctrl */ - uart->regs[CR] = RXE | TXE | UARTEN; + pl011_write(uart, CR, RXE | TXE | UARTEN); } static void __init pl011_init_postirq(struct serial_port *port) @@ -180,10 +182,10 @@ static void __init pl011_init_postirq(struct serial_port *port) } /* Clear pending error interrupts */ - uart->regs[ICR] = OEI|BEI|PEI|FEI; + pl011_write(uart, ICR, OEI|BEI|PEI|FEI); /* Unmask interrupts */ - uart->regs[IMSC] = RTI|DSRMI|DCDMI|CTSMI|RIMI; + pl011_write(uart, IMSC, RTI|DSRMI|DCDMI|CTSMI|RIMI); } static void pl011_suspend(struct serial_port *port) @@ -199,23 +201,25 @@ static void pl011_resume(struct serial_port *port) static unsigned int pl011_tx_ready(struct serial_port *port) { struct pl011 *uart = port->uart; - return uart->regs[FR] & TXFE ? 16 : 0; + + return ((pl011_read(uart, FR) & TXFE) ? 16 : 0); } static void pl011_putc(struct serial_port *port, char c) { struct pl011 *uart = port->uart; - uart->regs[DR] = (uint32_t) (unsigned char) c; + + pl011_write(uart, DR, (uint32_t)(unsigned char)c); } static int pl011_getc(struct serial_port *port, char *pc) { struct pl011 *uart = port->uart; - if ( uart->regs[FR] & RXFE ) + if ( pl011_read(uart, FR) & RXFE ) return 0; - *pc = uart->regs[DR] & 0xff; + *pc = pl011_read(uart, DR) & 0xff; return 1; }