From patchwork Tue Jul 23 18:05:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 18544 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-gh0-f199.google.com (mail-gh0-f199.google.com [209.85.160.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B3F9825E73 for ; Tue, 23 Jul 2013 18:05:22 +0000 (UTC) Received: by mail-gh0-f199.google.com with SMTP id g14sf9357288ghb.10 for ; Tue, 23 Jul 2013 11:05:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-beenthere:x-forwarded-to:x-forwarded-for:delivered-to:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe :content-type:content-transfer-encoding; bh=AmSsxOQZ9eDYqh0D5bSZjW6YTE+vpf7D6u4ciLnOgBM=; b=aQVLAWe3PtSwHJhFoq8Tm7UR2nTDn3VJjPmnUQ2YpCJQgmZSFv9GLy7Y1B8R7l9YxW BOByaM/oitUwW/zLDgW3XeOVZKM5vAwxaqpJLyeYP958KHaG1YqTfNawQPQWLtj+xq4C U9JNR1iiTy76c12onNcEsJKIjmK3RIbFqhzuX2LSt0hQfol394gXraCF5adWiq7bPuWJ +rXVdWtYSu4sSHppDa4qy9zcR/hCiiXvOBmawljQCCvFSMW4savHalG50S/P9lZaFOpP 0LSk3PXHKBXn0Qp8FqA2KbmSUMtcinVfKUDWIlSndGMF6HwWSuF0x+qKCe6c6scxAncD JFHg== X-Received: by 10.236.194.33 with SMTP id l21mr18834690yhn.42.1374602722496; Tue, 23 Jul 2013 11:05:22 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.133.102 with SMTP id pb6ls3181083qeb.80.gmail; Tue, 23 Jul 2013 11:05:22 -0700 (PDT) X-Received: by 10.220.17.206 with SMTP id t14mr12047425vca.15.1374602722401; Tue, 23 Jul 2013 11:05:22 -0700 (PDT) Received: from mail-ve0-f176.google.com (mail-ve0-f176.google.com [209.85.128.176]) by mx.google.com with ESMTPS id y4si7217966vcn.134.2013.07.23.11.05.22 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 23 Jul 2013 11:05:22 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.176; Received: by mail-ve0-f176.google.com with SMTP id c13so6375245vea.35 for ; Tue, 23 Jul 2013 11:05:22 -0700 (PDT) X-Received: by 10.220.83.69 with SMTP id e5mr9496615vcl.53.1374602722323; Tue, 23 Jul 2013 11:05:22 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.165.8 with SMTP id yu8csp120058veb; Tue, 23 Jul 2013 11:05:21 -0700 (PDT) X-Received: by 10.180.108.129 with SMTP id hk1mr22752376wib.42.1374602721088; Tue, 23 Jul 2013 11:05:21 -0700 (PDT) Received: from mail-we0-f169.google.com (mail-we0-f169.google.com [74.125.82.169]) by mx.google.com with ESMTPS id o1si1792859wia.2.2013.07.23.11.05.20 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 23 Jul 2013 11:05:21 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.169 is neither permitted nor denied by best guess record for domain of julien.grall@linaro.org) client-ip=74.125.82.169; Received: by mail-we0-f169.google.com with SMTP id n57so7506377wev.28 for ; Tue, 23 Jul 2013 11:05:20 -0700 (PDT) X-Received: by 10.180.185.101 with SMTP id fb5mr12565695wic.44.1374602720625; Tue, 23 Jul 2013 11:05:20 -0700 (PDT) Received: from belegaer.uk.xensource.com. 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[46.33.159.2]) by mx.google.com with ESMTPSA id iz8sm7692080wic.3.2013.07.23.11.05.19 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 23 Jul 2013 11:05:19 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: ian.campbell@citrix.com, Stefano.Stabellini@eu.citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH 3/3] xen/arm: errata 766422: decode thumb store during data abort Date: Tue, 23 Jul 2013 19:05:13 +0100 Message-Id: <1374602713-716-4-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1374602713-716-1-git-send-email-julien.grall@linaro.org> References: <1374602713-716-1-git-send-email-julien.grall@linaro.org> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmYHv1/0ExGGBfOlRYNwh9eWQfvXl5J1HvddEt1OEYNJBLq/6xSoS2TCcnVz+ydI/NgnExh X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , >From the errata document: When a non-secure non-hypervisor memory operation instruction generates a stage2 page table translation fault, a trap to the hypervisor will be triggered. For an architecturally defined subset of instructions, the Hypervisor Syndrome Register (HSR) will have the Instruction Syndrome Valid (ISV) bit set to 1’b1, and the Rt field should reflect the source register (for stores) or destination register for loads. On Cortex-A15, for Thumb and ThumbEE stores, the Rt value may be incorrect and should not be used, even if the ISV bit is set. All loads, and all ARM instruction set loads and stores, will have the correct Rt value if the ISV bit is set. To avoid this issue, Xen needs to decode thumb store instruction and update the transfer register. Signed-off-by: Julien Grall --- xen/arch/arm/traps.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index d6dc37d..da2bef6 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "io.h" #include "vtimer.h" @@ -996,6 +997,31 @@ done: if (first) unmap_domain_page(first); } +static int read_instruction(struct cpu_user_regs *regs, unsigned len, + uint32_t *instr) +{ + int rc; + + rc = raw_copy_from_guest(instr, (void * __user)regs->pc, len); + + if ( rc ) + return rc; + + switch ( len ) + { + /* 16-bit instruction */ + case 2: + *instr &= 0xffff; + break; + /* 32-bit instruction */ + case 4: + *instr = (*instr & 0xffff) << 16 | (*instr & 0xffff0000) >> 16; + break; + } + + return 0; +} + static void do_trap_data_abort_guest(struct cpu_user_regs *regs, struct hsr_dabt dabt) { @@ -1021,6 +1047,27 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs, if ( !dabt.valid ) goto bad_data_abort; + /* + * Errata 766422: Thumb store translation fault to Hypervisor may + * not have correct HSR Rt value. + */ + if ( (regs->cpsr & PSR_THUMB) && dabt.write ) + { + uint32_t instr = 0; + + rc = read_instruction(regs, dabt.len ? 4 : 2, &instr); + if ( rc ) + goto bad_data_abort; + + /* Retrieve the transfer register from the instruction */ + if ( dabt.len ) + /* With 32-bit store instruction, the register is in [12..15] */ + info.dabt.reg = (instr & 0xf000) >> 12; + else + /* With 16-bit store instruction, the register is in [0..3] */ + info.dabt.reg = instr & 0x7; + } + if (handle_mmio(&info)) { regs->pc += dabt.len ? 4 : 2;