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[46.33.159.2]) by mx.google.com with ESMTPSA id iz8sm7692080wic.3.2013.07.23.11.05.17 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 23 Jul 2013 11:05:18 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: ian.campbell@citrix.com, Stefano.Stabellini@eu.citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH 2/3] xen/arm: Allow secondary cpus to start in THUMB Date: Tue, 23 Jul 2013 19:05:12 +0100 Message-Id: <1374602713-716-3-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1374602713-716-1-git-send-email-julien.grall@linaro.org> References: <1374602713-716-1-git-send-email-julien.grall@linaro.org> X-Gm-Message-State: ALoCoQlh9+Cn4t8fRY9v/rO/HjtftmnbvRbloXg8+fvOkXlE9fJ6rUHiICRctm2DlnaPPH/Yb1Yi X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.46 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Unlike bx, eret will not update the instruction set (THUMB,ARM) according to the return address. This will result to an unpredicable behaviour for the processor if the address doesn't match the right instruction set. When the kernel is compiled with THUMB2, THUMB bit needs to be set in CPSR for the secondary cpus. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- xen/arch/arm/psci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 18feead..574c343 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -43,6 +43,9 @@ int do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) ctxt->ttbr1 = 0; ctxt->ttbcr = 0; /* Defined Reset Value */ ctxt->user_regs.cpsr = PSR_GUEST_INIT; + /* Start the VCPU in THUMB mode if it's requested by the kernel */ + if ( entry_point & 1 ) + ctxt->user_regs.cpsr |= PSR_THUMB; ctxt->flags = VGCF_online; domain_lock(d);