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[46.33.159.2]) by mx.google.com with ESMTPSA id fo10sm9469637wib.8.2013.06.28.04.26.08 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 28 Jun 2013 04:26:09 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: ian.campbell@citrix.com, Stefano.Stabellini@eu.citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH] xen/arm: gic_shutdown_irq must only disable the right IRQ Date: Fri, 28 Jun 2013 12:25:57 +0100 Message-Id: <1372418757-19213-1-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQm2x71X8xpQhn5Zxhv2iUNoid+SKU4TYJFjH0GllVsu3j2Pg4MB5tiMb/rCPBBW6VIEsEzt X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.45 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , When GICD_ICENABLERn is read, all the 1s bit represent enabled IRQs. Currently gic_shutdown_irq: - read GICD_ICENABLER - set the corresping bit to 1 - write back the new value That means, Xen will disable more IRQs than necessary. Signed-off-by: Julien Grall Acked-by: Ian Campbell Signed-off-by: Stefano Stabellini --- xen/arch/arm/gic.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 177560e..cafb681 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -117,12 +117,10 @@ static unsigned int gic_irq_startup(struct irq_desc *desc) static void gic_irq_shutdown(struct irq_desc *desc) { - uint32_t enabler; int irq = desc->irq; /* Disable routing */ - enabler = GICD[GICD_ICENABLER + irq / 32]; - GICD[GICD_ICENABLER + irq / 32] = enabler | (1u << (irq % 32)); + GICD[GICD_ICENABLER + irq / 32] = (1u << (irq % 32)); } static void gic_irq_enable(struct irq_desc *desc)