From patchwork Fri May 10 02:18:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 16844 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-gg0-f197.google.com (mail-gg0-f197.google.com [209.85.161.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id CAA6E238F7 for ; Fri, 10 May 2013 02:20:13 +0000 (UTC) Received: by mail-gg0-f197.google.com with SMTP id w6sf3745654ggk.8 for ; Thu, 09 May 2013 19:19:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:mime-version:x-beenthere:x-received:received-spf :x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=VS54gzfR/otx/RRcBLn1Ym2ToVl6xl5NNqKaQ7oRBZs=; b=gL3rlqtgPEoRSUvyADbhAxPPo8SR9vxNZk7SnL8FjmtBHW6A4k++PTip9zytTcRKVu SzTBv9nkqdKpBab6nWzNF2hkjbMU2QE1DbfHO0vwJe48ihZAdZW54ic5ZLkkOjFOvj5I CIRs/bjVWHE7efW/Y0Jl71PXZ70FvaNkMhvmrh2CopEa49UiXwbSWObwFZgIZjjjVYfC ki9huD1EN2LWMEfGLVZ6Td8JGtn9y65SyOnAqIzv7x61vc4GX1bk+jcIEITaG+CNi8D3 yJGFmpcFemZFGiwwR11Lseoy84FaOmCa43vRSPs0ZmNvPpggl8iriA/8mfBFiQ6m6ck+ tbgg== X-Received: by 10.224.215.194 with SMTP id hf2mr11108793qab.0.1368152389167; Thu, 09 May 2013 19:19:49 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.121.5 with SMTP id lg5ls1667138qeb.21.gmail; Thu, 09 May 2013 19:19:48 -0700 (PDT) X-Received: by 10.52.0.198 with SMTP id 6mr2507144vdg.65.1368152388903; Thu, 09 May 2013 19:19:48 -0700 (PDT) Received: from mail-vb0-x22c.google.com (mail-vb0-x22c.google.com [2607:f8b0:400c:c02::22c]) by mx.google.com with ESMTPS id ir6si354419vdb.26.2013.05.09.19.19.48 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 19:19:48 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400c:c02::22c is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c02::22c; Received: by mail-vb0-f44.google.com with SMTP id e13so3099757vbg.31 for ; Thu, 09 May 2013 19:19:48 -0700 (PDT) X-Received: by 10.58.227.104 with SMTP id rz8mr9686769vec.22.1368152388611; Thu, 09 May 2013 19:19:48 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.217.15 with SMTP id hk15csp36243vcb; Thu, 9 May 2013 19:19:47 -0700 (PDT) X-Received: by 10.194.90.108 with SMTP id bv12mr21625008wjb.4.1368152387454; Thu, 09 May 2013 19:19:47 -0700 (PDT) Received: from mail-wi0-x230.google.com (mail-wi0-x230.google.com [2a00:1450:400c:c05::230]) by mx.google.com with ESMTPS id uz5si170379wjc.50.2013.05.09.19.19.46 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 19:19:47 -0700 (PDT) Received-SPF: neutral (google.com: 2a00:1450:400c:c05::230 is neither permitted nor denied by best guess record for domain of julien.grall@linaro.org) client-ip=2a00:1450:400c:c05::230; Received: by mail-wi0-f176.google.com with SMTP id hr14so153006wib.15 for ; Thu, 09 May 2013 19:19:46 -0700 (PDT) X-Received: by 10.194.179.69 with SMTP id de5mr5577111wjc.38.1368152386751; Thu, 09 May 2013 19:19:46 -0700 (PDT) Received: from belegaer.uk.xensource.com. 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[46.33.159.2]) by mx.google.com with ESMTPSA id dj7sm597075wib.6.2013.05.09.19.19.45 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 19:19:46 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: Stefano.Stabellini@eu.citrix.com, ian.campbell@citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH V3 32/41] xen/arm: WORKAROUND 1:1 memory mapping for dom0 Date: Fri, 10 May 2013 03:18:18 +0100 Message-Id: <1368152307-598-33-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1368152307-598-1-git-send-email-julien.grall@linaro.org> References: <1368152307-598-1-git-send-email-julien.grall@linaro.org> X-Gm-Message-State: ALoCoQknDY1Y0YM2vabsMnDzA14oh9t3OU4IQthFSsrk509KNKc0zAflr05v+cvKH271hpmU5918 X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::22c is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Currently xen doesn't implement SYS MMU. When a device will talk with dom0 with DMA request the domain will use GFN instead of MFN. For instance on the arndale board, without this patch the network doesn't work. The 1:1 mapping is a workaround and MUST be remove as soon as a SYS MMU is implemented in XEN. Signed-off-by: Julien Grall Acked-by: Ian Campbell Changes in v2: - Add quirk in platform code to only enable 1:1 mapping if the board really need it to run (ie: SYS MMU is not yet implemented in Xen). --- xen/arch/arm/domain_build.c | 41 ++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/platform.h | 6 ++++++ 2 files changed, 47 insertions(+) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 75c3006..8369099 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -62,6 +62,43 @@ struct vcpu *__init alloc_dom0_vcpu0(void) return alloc_vcpu(dom0, 0, 0); } +static int set_memory_reg_11(struct domain *d, struct kernel_info *kinfo, + const void *fdt, const u32 *cell, int len, + int address_cells, int size_cells, u32 *new_cell) +{ + int reg_size = (address_cells + size_cells) * sizeof(*cell); + paddr_t start; + paddr_t size; + struct page_info *pg; + unsigned int order = get_order_from_bytes(dom0_mem); + int res; + paddr_t spfn; + + pg = alloc_domheap_pages(d, order, 0); + if ( !pg ) + panic("Failed to allocate contiguous memory for dom0\n"); + + spfn = page_to_mfn(pg); + start = spfn << PAGE_SHIFT; + size = (1 << order) << PAGE_SHIFT; + + // 1:1 mapping + printk("Populate P2M %#"PRIx64"->%#"PRIx64" (1:1 mapping for dom0)\n", + start, start + size); + res = guest_physmap_add_page(d, spfn, spfn, order); + + if ( res ) + panic("Unable to add pages in DOM0: %d\n", res); + + device_tree_set_reg(&new_cell, address_cells, size_cells, start, size); + + kinfo->mem.bank[0].start = start; + kinfo->mem.bank[0].size = size; + kinfo->mem.nr_banks = 1; + + return reg_size; +} + static int set_memory_reg(struct domain *d, struct kernel_info *kinfo, const void *fdt, const u32 *cell, int len, int address_cells, int size_cells, u32 *new_cell) @@ -71,6 +108,10 @@ static int set_memory_reg(struct domain *d, struct kernel_info *kinfo, u64 start; u64 size; + if ( platform_has_quirk(PLATFORM_QUIRK_DOM0_MAPPING_11) ) + return set_memory_reg_11(d, kinfo, fdt, cell, len, address_cells, + size_cells, new_cell); + while ( kinfo->unassigned_mem > 0 && l + reg_size <= len && kinfo->mem.nr_banks < NR_MEM_BANKS ) { diff --git a/xen/include/asm-arm/platform.h b/xen/include/asm-arm/platform.h index e116265..f460e9c 100644 --- a/xen/include/asm-arm/platform.h +++ b/xen/include/asm-arm/platform.h @@ -28,6 +28,12 @@ struct platform_desc { uint32_t (*quirks)(void); }; +/* + * Quirk to map dom0 memory in 1:1 + * Usefull on platform where System MMU is not yet implemented + */ +#define PLATFORM_QUIRK_DOM0_MAPPING_11 (1 << 0) + int __init platform_init(void); int __init platform_init_time(void); int __init platform_specific_mapping(struct domain *d);