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[46.33.159.2]) by mx.google.com with ESMTPSA id dj7sm597075wib.6.2013.05.09.19.19.36 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 19:19:36 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: Stefano.Stabellini@eu.citrix.com, ian.campbell@citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH V3 25/41] xen/arm: Don't hardcode virtual timer IRQs Date: Fri, 10 May 2013 03:18:11 +0100 Message-Id: <1368152307-598-26-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1368152307-598-1-git-send-email-julien.grall@linaro.org> References: <1368152307-598-1-git-send-email-julien.grall@linaro.org> X-Gm-Message-State: ALoCoQnS/lHd201D4Gu2ip8f5Nr17TraVZ74lvDbeOwJnqrrKj50WLmCUNTK5UbZOl722c/lyUXn X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::22f is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Define virtual timer IRQs per VCPU Signed-off-by: Julien Grall Acked-by: Ian Campbell --- xen/arch/arm/time.c | 9 ++++++++- xen/arch/arm/vtimer.c | 13 ++++++++----- xen/include/asm-arm/time.h | 3 +++ 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index ecb7626..2e928bc 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -49,6 +49,13 @@ unsigned long __read_mostly cpu_khz; /* CPU clock frequency in kHz. */ static struct dt_irq timer_irq[MAX_TIMER_PPI]; +const struct dt_irq *timer_dt_irq(enum timer_ppi ppi) +{ + ASSERT(ppi >= TIMER_PHYS_SECURE_PPI && ppi < MAX_TIMER_PPI); + + return &timer_irq[ppi]; +} + /*static inline*/ s_time_t ticks_to_ns(uint64_t ticks) { return muldiv64(ticks, SECONDS(1), 1000 * cpu_khz); @@ -192,7 +199,7 @@ static void vtimer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) { current->arch.virt_timer.ctl = READ_SYSREG32(CNTV_CTL_EL0); WRITE_SYSREG32(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_EL0); - vgic_vcpu_inject_irq(current, irq, 1); + vgic_vcpu_inject_irq(current, current->arch.virt_timer.irq, 1); } /* Route timer's IRQ on this CPU */ diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 6993425..aee762a 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -34,14 +34,14 @@ static void phys_timer_expired(void *data) struct vtimer *t = data; t->ctl |= CNTx_CTL_PENDING; if ( !(t->ctl & CNTx_CTL_MASK) ) - vgic_vcpu_inject_irq(t->v, 30, 1); + vgic_vcpu_inject_irq(t->v, t->irq, 1); } static void virt_timer_expired(void *data) { struct vtimer *t = data; t->ctl |= CNTx_CTL_MASK; - vgic_vcpu_inject_irq(t->v, 27, 1); + vgic_vcpu_inject_irq(t->v, t->irq, 1); } int vcpu_domain_init(struct domain *d) @@ -55,17 +55,20 @@ int vcpu_vtimer_init(struct vcpu *v) { struct vtimer *t = &v->arch.phys_timer; + /* TODO: Retrieve physical and virtual timer IRQ from the guest + * DT. For the moment we use dom0 DT + */ + init_timer(&t->timer, phys_timer_expired, t, v->processor); t->ctl = 0; t->cval = NOW(); - t->irq = 30; + t->irq = timer_dt_irq(TIMER_PHYS_NONSECURE_PPI)->irq; t->v = v; t = &v->arch.virt_timer; init_timer(&t->timer, virt_timer_expired, t, v->processor); t->ctl = 0; - t->cval = 0; - t->irq = 27; + t->irq = timer_dt_irq(TIMER_VIRT_PPI)->irq; t->v = v; return 0; diff --git a/xen/include/asm-arm/time.h b/xen/include/asm-arm/time.h index 05833ce..f7aa868 100644 --- a/xen/include/asm-arm/time.h +++ b/xen/include/asm-arm/time.h @@ -21,6 +21,9 @@ enum timer_ppi MAX_TIMER_PPI = 4, }; +/* Get one of the timer IRQ description */ +const struct dt_irq* timer_dt_irq(enum timer_ppi ppi); + /* Route timer's IRQ on this CPU */ extern void __cpuinit route_timer_interrupt(void);