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[46.33.159.2]) by mx.google.com with ESMTPSA id dj7sm597075wib.6.2013.05.09.19.19.28 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 19:19:29 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: Stefano.Stabellini@eu.citrix.com, ian.campbell@citrix.com, patches@linaro.org, Julien Grall Subject: [PATCH V3 19/41] xen/arm: Introduce gic_irq_xlate Date: Fri, 10 May 2013 03:18:05 +0100 Message-Id: <1368152307-598-20-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1368152307-598-1-git-send-email-julien.grall@linaro.org> References: <1368152307-598-1-git-send-email-julien.grall@linaro.org> X-Gm-Message-State: ALoCoQl0xzvXII2/DLogZ+CKNW21oCAxyXvlGyqTBHCbtZroH2LPjSJxY9+cok6eHg/Bi3OGTJz8 X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This function translates an interrupt specifier to an IRQ number and IRQ type (ie: level trigger, edge trigger,...). It's GIC specific. Signed-off-by: Julien Grall Acked-by: Ian Campbell Changes in v2: - Use DT_IRQ_TYPE_SENSE_MASK instead of IRQ_TYPE_SENSE_MASK --- xen/arch/arm/gic.c | 20 ++++++++++++++++++++ xen/arch/arm/setup.c | 1 + xen/include/asm-arm/gic.h | 4 ++++ 3 files changed, 25 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 06ba78c..6f57d66 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -329,6 +329,26 @@ static void __cpuinit gic_hyp_disable(void) GICH[GICH_HCR] = 0; } +int gic_irq_xlate(const u32 *intspec, unsigned int intsize, + unsigned int *out_hwirq, + unsigned int *out_type) +{ + if ( intsize < 3 ) + return -EINVAL; + + /* Get the interrupt number and add 16 to skip over SGIs */ + *out_hwirq = intspec[1] + 16; + + /* For SPIs, we need to add 16 more to get the GIC irq ID number */ + if ( !intspec[0] ) + *out_hwirq += 16; + + if ( out_type ) + *out_type = intspec[2] & DT_IRQ_TYPE_SENSE_MASK; + + return 0; +} + /* Set up the GIC */ void __init gic_init(void) { diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 81bc956..fc53117 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -431,6 +431,7 @@ void __init start_xen(unsigned long boot_phys_offset, vm_init(); dt_unflatten_host_device_tree(); + dt_irq_xlate = gic_irq_xlate; #ifdef EARLY_UART_ADDRESS /* TODO Need to get device tree or command line for UART address */ diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 78dd21a..6ff217c 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -189,6 +189,10 @@ extern void send_SGI_allbutself(enum gic_sgi sgi); /* print useful debug info */ extern void gic_dump_info(struct vcpu *v); +/* IRQ translation function for the device tree */ +int gic_irq_xlate(const u32 *intspec, unsigned int intsize, + unsigned int *out_hwirq, unsigned int *out_type); + #endif /* __ASSEMBLY__ */ #endif