From patchwork Tue Oct 16 10:54:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 12266 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0F17923F62 for ; Tue, 16 Oct 2012 10:54:14 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id ACD4FA18691 for ; Tue, 16 Oct 2012 10:54:13 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so9229664iej.11 for ; Tue, 16 Oct 2012 03:54:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=JwSzDtkXFpVUBYjKZlPQyiimL9/64Hq2Ocif+5Mjakk=; b=Vir0RQukzPmrmKwqjZ6lGr7IK4H0+4QGOTiOe0a3msuC4g1dLsWZOGS4VsqWlRBm86 IZFLB2TXfjalw32VHjI03rpUnnfpc5eOgAkzhNgi1B1sJR70PSfKZfMJ84zwTYahYW0l QTzDMxUgPpvah4YeHAXNhVgAXbhoJ2kYLVQ8cXbiYDNnAf2rfkGhsoBbdmSvJZXpMGB/ 1sCQRPJlkTm11r4DKAi2/Ymb71Ggrvh+Dt724zLr76tshaxzIDdGecY/vPcVJtNf9tOA jiFBd43T0TY7d+YuMmCKFVmc27GNwgM5vRTzQmlER81LiHDhYFQsJTka4xt78OYm2+sn NZ5Q== Received: by 10.50.87.134 with SMTP id ay6mr11407993igb.70.1350384853029; Tue, 16 Oct 2012 03:54:13 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp707768igt; Tue, 16 Oct 2012 03:54:12 -0700 (PDT) Received: by 10.112.84.131 with SMTP id z3mr5358371lby.70.1350384851316; Tue, 16 Oct 2012 03:54:11 -0700 (PDT) Received: from mail-lb0-f178.google.com (mail-lb0-f178.google.com [209.85.217.178]) by mx.google.com with ESMTPS id ig6si11881540lab.30.2012.10.16.03.54.10 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 16 Oct 2012 03:54:11 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.217.178 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=209.85.217.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.217.178 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by mail-lb0-f178.google.com with SMTP id o2so5113469lba.37 for ; Tue, 16 Oct 2012 03:54:10 -0700 (PDT) Received: by 10.112.38.67 with SMTP id e3mr5326869lbk.98.1350384850512; Tue, 16 Oct 2012 03:54:10 -0700 (PDT) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id ti4sm5379595lab.1.2012.10.16.03.54.08 (version=SSLv3 cipher=OTHER); Tue, 16 Oct 2012 03:54:09 -0700 (PDT) From: Dave Martin To: patches@arm.linux.org.uk Cc: patches@linaro.org, Dave Martin Subject: [PATCH] ARM: proc-v7: Ensure correct instruction set after cpu_reset Date: Tue, 16 Oct 2012 11:54:00 +0100 Message-Id: <1350384840-28415-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-Gm-Message-State: ALoCoQnCnpqzSZ5YpcM7nW+Fq+tF+PsbnTDMiv1yIeyARJRubtRsboYF4yjdSdgqB7YkYFYFamf7 Because mov pc, never switches instruction set when executed in Thumb code, Thumb-2 kernels will silently execute the target code after cpu_reset as Thumb code, even if the passed code pointer denotes ARM (bit 0 clear). This patch uses bx instead, ensuring the correct instruction set for the target code. Thumb code in the kernel is not supported prior to ARMv7, so other CPUs are not affected. Signed-off-by: Dave Martin Acked-by: Will Deacon Acked-by: Nicolas Pitre --- KernelVersion: 3.7-rc1 diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 846d279..42cc833 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -57,7 +57,7 @@ ENTRY(cpu_v7_reset) THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) mcr p15, 0, r1, c1, c0, 0 @ disable MMU isb - mov pc, r0 + bx r0 ENDPROC(cpu_v7_reset) .popsection