From patchwork Wed Feb 15 18:15:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 6795 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C546623DE1 for ; Wed, 15 Feb 2012 18:16:19 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 95CFDA189B1 for ; Wed, 15 Feb 2012 18:16:19 +0000 (UTC) Received: by yhgm50 with SMTP id m50so1030683yhg.11 for ; Wed, 15 Feb 2012 10:16:19 -0800 (PST) Received: by 10.50.184.168 with SMTP id ev8mr43399670igc.29.1329329778920; Wed, 15 Feb 2012 10:16:18 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.80.19 with SMTP id r19cs2656ibk; Wed, 15 Feb 2012 10:16:18 -0800 (PST) Received: by 10.180.81.66 with SMTP id y2mr36825131wix.20.1329329777739; Wed, 15 Feb 2012 10:16:17 -0800 (PST) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id k49si3197141wed.2.2012.02.15.10.16.16 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 15 Feb 2012 10:16:17 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by mail-ww0-f50.google.com with SMTP id dq11so1215859wgb.31 for ; Wed, 15 Feb 2012 10:16:16 -0800 (PST) MIME-Version: 1.0 Received: by 10.180.102.35 with SMTP id fl3mr36757388wib.22.1329329776777; Wed, 15 Feb 2012 10:16:16 -0800 (PST) Received: from localhost.localdomain ([213.123.120.124]) by mx.google.com with ESMTPS id dw7sm35106696wib.4.2012.02.15.10.16.14 (version=SSLv3 cipher=OTHER); Wed, 15 Feb 2012 10:16:16 -0800 (PST) From: Dave Martin To: Nicolas Pitre , Christoffer Dall , Marc Zyngier , Will Deacon Cc: patches@linaro.org, Dave Martin Subject: [PATCH 01/10] ARM: head: Tidy up CPU mode setting on kernel entry Date: Wed, 15 Feb 2012 18:15:54 +0000 Message-Id: <1329329763-31508-2-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1329329763-31508-1-git-send-email-dave.martin@linaro.org> References: <1329329763-31508-1-git-send-email-dave.martin@linaro.org> X-Gm-Message-State: ALoCoQkt4X0qU/LNISfHw/+GAsMJjCdLmY3ESusCcjPiYSZGWdKFnOv4v9YpYGGBmJZ5u8P47OgV This patch does two things: * Ensure that asynchronous aborts are masked at kernel entry. The bootloader should be masking these anyway, but this reduces the damage window just in case it doesn't. * Enter svc mode via exception return to ensure that CPU state is properly serialised. This does not matter when switching from an ordinary privileged mode ("PL1" modes in ARMv7-AR rev C parlance), but it potentially does matter when switching from a another privileged mode such as hyp mode. This should allow the kernel to boot safely either from svc mode or hyp mode, even if no support for use of the ARM Virtualization Extensions is built into the kernel. Signed-off-by: Dave Martin --- arch/arm/kernel/head.S | 23 ++++++++++++++++++++--- 1 files changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 6d57911..0ccf042 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -64,6 +64,21 @@ #endif /* + * Helper macro to enter SVC mode cleanly and mask interrupts. reg is a + * scratch register available for the macro to overwrite. + */ +.macro safe_svcmode_maskall reg:req + mrs \reg , cpsr + orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT + bic \reg , \reg , #MODE_MASK + orr \reg , \reg , #SVC_MODE + msr spsr_cxsf, \reg + adr \reg , BSYM(1f) + movs pc, \reg +1: +.endm + +/* * Kernel startup entry point. * --------------------------- * @@ -91,8 +106,9 @@ ENTRY(stext) THUMB( .thumb ) @ switch to Thumb now. THUMB(1: ) - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode - @ and irqs disabled + @ ensure svc mode and all interrupts masked + safe_svcmode_maskall r4 + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? @@ -346,7 +362,8 @@ ENTRY(secondary_startup) * the processor type - there is no need to check the machine type * as it has already been validated by the primary processor. */ - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 + safe_svcmode_maskall r4 + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type movs r10, r5 @ invalid processor?