From patchwork Fri Feb 10 19:18:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 6755 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D994823F8D for ; Fri, 10 Feb 2012 19:16:21 +0000 (UTC) Received: from mail-tul01m020-f180.google.com (mail-tul01m020-f180.google.com [209.85.214.180]) by fiordland.canonical.com (Postfix) with ESMTP id 9B24FA186E1 for ; Fri, 10 Feb 2012 19:16:21 +0000 (UTC) Received: by obbuo19 with SMTP id uo19so5627671obb.11 for ; Fri, 10 Feb 2012 11:16:21 -0800 (PST) Received: by 10.50.15.231 with SMTP id a7mr13477952igd.8.1328901380914; Fri, 10 Feb 2012 11:16:20 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.12.131 with SMTP id x3cs89849ibx; Fri, 10 Feb 2012 11:16:20 -0800 (PST) Received: by 10.101.180.33 with SMTP id h33mr3449985anp.43.1328901379893; Fri, 10 Feb 2012 11:16:19 -0800 (PST) Received: from mail-gx0-f178.google.com (mail-gx0-f178.google.com [209.85.161.178]) by mx.google.com with ESMTPS id f29si3346665anj.164.2012.02.10.11.16.18 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 10 Feb 2012 11:16:19 -0800 (PST) Received-SPF: neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=209.85.161.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by ggmi4 with SMTP id i4so2002731ggm.37 for ; Fri, 10 Feb 2012 11:16:18 -0800 (PST) MIME-Version: 1.0 Received: by 10.50.149.162 with SMTP id ub2mr14004202igb.1.1328901378284; Fri, 10 Feb 2012 11:16:18 -0800 (PST) Received: from LinaroE102765.static.wiline.com ([108.60.102.133]) by mx.google.com with ESMTPS id wn7sm3769979igc.0.2012.02.10.11.16.16 (version=SSLv3 cipher=OTHER); Fri, 10 Feb 2012 11:16:17 -0800 (PST) From: Dave Martin To: Nicolas Pitre , Christoffer Dall , Marc Zyngier , Will Deacon Cc: patches@linaro.org, Dave Martin Subject: [PATCH 1/2] ARM: head: Tidy up CPU mode setting on kernel entry Date: Fri, 10 Feb 2012 11:18:27 -0800 Message-Id: <1328901508-22076-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.5.4 X-Gm-Message-State: ALoCoQliZpzZ/YsrOF2vg+rsLcQ/3CBIRMLtrxepJdUR+9Ls1X6qnlXaUOlJOV8ocidZyJxCS1ok This patch does two things: * Ensure that asynchronous aborts are masked at kernel entry. The bootloader should be masking these anyway, but this reduces the damage window just in case it doesn't. * Enter svc mode via exception return to ensure that CPU state is properly serialised. This does not matter when switching from an ordinary privileged mode ("PL1" modes in ARMv7-AR rev C parlance), but it potentially does matter when switching from a another privileged mode such as hyp mode. This should allow the kernel to boot safely either from svc mode or hyp mode, even if no support for use of the ARM Virtualization Extensions is built into the kernel. Signed-off-by: Dave Martin --- arch/arm/kernel/head.S | 23 ++++++++++++++++++++--- 1 files changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 6d57911..0ccf042 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -64,6 +64,21 @@ #endif /* + * Helper macro to enter SVC mode cleanly and mask interrupts. reg is a + * scratch register available for the macro to overwrite. + */ +.macro safe_svcmode_maskall reg:req + mrs \reg , cpsr + orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT + bic \reg , \reg , #MODE_MASK + orr \reg , \reg , #SVC_MODE + msr spsr_cxsf, \reg + adr \reg , BSYM(1f) + movs pc, \reg +1: +.endm + +/* * Kernel startup entry point. * --------------------------- * @@ -91,8 +106,9 @@ ENTRY(stext) THUMB( .thumb ) @ switch to Thumb now. THUMB(1: ) - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode - @ and irqs disabled + @ ensure svc mode and all interrupts masked + safe_svcmode_maskall r4 + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? @@ -346,7 +362,8 @@ ENTRY(secondary_startup) * the processor type - there is no need to check the machine type * as it has already been validated by the primary processor. */ - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 + safe_svcmode_maskall r4 + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type movs r10, r5 @ invalid processor?