From patchwork Tue Sep 17 18:12:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 173914 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1463308ill; Tue, 17 Sep 2019 11:14:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqyoelhlhrwJRVCZdXUwg4MjSo3tIgeAeNxWVJnLa2HFvISFOL3YtqkK8h+Ci8nK8lsi2vm0 X-Received: by 2002:a6b:3b4a:: with SMTP id i71mr64598ioa.258.1568744074879; Tue, 17 Sep 2019 11:14:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568744074; cv=none; d=google.com; s=arc-20160816; b=QW0A/Ued58O1ne58I5vS/6zU3zBQDmNREuKH9VCVsbA03JEaUFDcV2lY992iuXW3Lm SYJMQs0caIQdCMmcnH8akMp3IDlTbLJf+DT/XZt8aPoI1bjDMZNJTdSi593AzZyVo8ln ZPMzdMjM/cXg6lVVuqNDSQ8lbnuQ6eb2DQkrwzBXO89D/y6kvqW0Pc4NqtDsWflPc3ir D6OS8+ktaUJ91Ngkv6Pdzt3GtG+DOGn0Vg0sXqMhSO3wUk2pT5AqGwKcJ15zzyiLRQ5q iv62unJMtKzIls5bVRQr7QElp3kMcoH+4GeGOkIKgzalDZ541/3jhCVHSDqawCZapcMo +x5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=OnaxXolAF/k4Wo0pAl49X731H+fnwT+HMnNTsfiiSX8=; b=PPGJOittPxh/YxIL2QXBufYM1g3C5Hh/fN5Gy812+kirwk+C5aYnYcypodjB+As6X5 iGVIicJIXNX8qGWUemTTyNDCbZd/HsaI7z54A3hBg8hxRqXXa2aCDQfANz86iLUHpSaw B8pXnO39F+fgihq6xY0Ad0N6vM8AC1gen+4p5ooUl+R7nOYUn//dwidtivgEAcoY1quP ki2SlWxvPXoX0/HTbwlpyZgoYaEQ46cuVU2unYhcI9E1OTDIVMyh6Ub87NG2bCrsrlOn cBUmu0ZexCFSEFYwKiHuvVzFkcgRneLKI3EW0/rwQ28Rmot1hrdcX15L/ZL1Y3C3Voew vobQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id g13si4180873jah.37.2019.09.17.11.14.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 17 Sep 2019 11:14:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iAHyR-0008Dd-Vp; Tue, 17 Sep 2019 18:13:11 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iAHyR-0008Cf-4B for xen-devel@lists.xenproject.org; Tue, 17 Sep 2019 18:13:11 +0000 X-Inumbo-ID: c677c192-d976-11e9-b76c-bc764e2007e4 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id c677c192-d976-11e9-b76c-bc764e2007e4; Tue, 17 Sep 2019 18:12:57 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D76751000; Tue, 17 Sep 2019 11:12:56 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 31F303F67D; Tue, 17 Sep 2019 11:12:56 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 17 Sep 2019 19:12:41 +0100 Message-Id: <20190917181244.30027-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190917181244.30027-1-julien.grall@arm.com> References: <20190917181244.30027-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v4 5/8] xen/arm64: head: Introduce macros to create table and mapping entry X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, any update to the boot-pages are open-coded. This is making more difficult to understand the logic of a function as each update roughly requires 6 instructions. To ease the readability, two new macros are introduced: - create_table_entry: Create a page-table entry in a given table. This can work at any level. - create_mapping_entry: Create a mapping entry in a given table. None of the users will require to map at any other level than 3rd (i.e page granularity). So the macro is only supporting 3rd level mapping. Furthermore, the two macros are capable to work independently of the state of the MMU. Lastly, take the opportunity to replace open-coded version in setup_fixmap() by the two new macros. The ones in create_page_tables() will be replaced in a follow-up patch. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v4: - Fix typo - /tlb/ptlb/ in create_mapping_entry macro Changes in v3: - Patch added --- xen/arch/arm/arm64/head.S | 83 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 67 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 177cec4e45..2cce342217 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -492,6 +492,68 @@ cpu_init: ENDPROC(cpu_init) /* + * Macro to create a page table entry in \ptbl to \tbl + * + * ptbl: table symbol where the entry will be created + * tbl: table symbol to point to + * virt: virtual address + * shift: #imm page table shift + * tmp1: scratch register + * tmp2: scratch register + * tmp3: scratch register + * + * Preserves \virt + * Clobbers \tmp1, \tmp2, \tmp3 + * + * Also use x20 for the phys offset. + * + * Note that all parameters using registers should be distinct. + */ +.macro create_table_entry, ptbl, tbl, virt, shift, tmp1, tmp2, tmp3 + lsr \tmp1, \virt, #\shift + and \tmp1, \tmp1, #LPAE_ENTRY_MASK/* \tmp1 := slot in \tlb */ + + load_paddr \tmp2, \tbl + mov \tmp3, #PT_PT /* \tmp3 := right for linear PT */ + orr \tmp3, \tmp3, \tmp2 /* + \tlb paddr */ + + adr_l \tmp2, \ptbl + + str \tmp3, [\tmp2, \tmp1, lsl #3] +.endm + +/* + * Macro to create a mapping entry in \tbl to \phys. Only mapping in 3rd + * level table (i.e page granularity) is supported. + * + * ptbl: table symbol where the entry will be created + * virt: virtual address + * phys: physical address (should be page aligned) + * tmp1: scratch register + * tmp2: scratch register + * tmp3: scratch register + * type: mapping type. If not specified it will be normal memory (PT_MEM_L3) + * + * Preserves \virt, \phys + * Clobbers \tmp1, \tmp2, \tmp3 + * + * Note that all parameters using registers should be distinct. + */ +.macro create_mapping_entry, ptbl, virt, phys, tmp1, tmp2, tmp3, type=PT_MEM_L3 + and \tmp3, \phys, #THIRD_MASK /* \tmp3 := PAGE_ALIGNED(phys) */ + + lsr \tmp1, \virt, #THIRD_SHIFT + and \tmp1, \tmp1, #LPAE_ENTRY_MASK/* \tmp1 := slot in \tlb */ + + mov \tmp2, #\type /* \tmp2 := right for section PT */ + orr \tmp2, \tmp2, \tmp3 /* + PAGE_ALIGNED(phys) */ + + adr_l \tmp3, \ptbl + + str \tmp2, [\tmp3, \tmp1, lsl #3] +.endm + +/* * Rebuild the boot pagetable's first-level entries. The structure * is described in mm.c. * @@ -731,28 +793,17 @@ ENDPROC(remove_identity_mapping) * x20: Physical offset * x23: Early UART base physical address * - * Clobbers x1 - x4 + * Clobbers x0 - x3 */ setup_fixmap: #ifdef CONFIG_EARLY_PRINTK /* Add UART to the fixmap table */ - ldr x1, =xen_fixmap /* x1 := vaddr (xen_fixmap) */ - lsr x2, x23, #THIRD_SHIFT - lsl x2, x2, #THIRD_SHIFT /* 4K aligned paddr of UART */ - mov x3, #PT_DEV_L3 - orr x2, x2, x3 /* x2 := 4K dev map including UART */ - str x2, [x1, #(FIXMAP_CONSOLE*8)] /* Map it in the first fixmap's slot */ + ldr x0, =EARLY_UART_VIRTUAL_ADDRESS + create_mapping_entry xen_fixmap, x0, x23, x1, x2, x3, type=PT_DEV_L3 #endif - /* Map fixmap into boot_second */ - ldr x4, =boot_second /* x4 := vaddr (boot_second) */ - load_paddr x2, xen_fixmap - mov x3, #PT_PT - orr x2, x2, x3 /* x2 := table map of xen_fixmap */ - ldr x1, =FIXMAP_ADDR(0) - lsr x1, x1, #(SECOND_SHIFT - 3) /* x1 := Slot for FIXMAP(0) */ - str x2, [x4, x1] /* Map it in the fixmap's slot */ - + ldr x0, =FIXMAP_ADDR(0) + create_table_entry boot_second, xen_fixmap, x0, SECOND_SHIFT, x1, x2, x3 /* Ensure any page table updates made above have occurred. */ dsb nshst