From patchwork Mon Jul 22 21:39:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 169442 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp8012415ilk; Mon, 22 Jul 2019 14:41:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqyLJUeRA+WNDhd+Tiy5LydYtoeDx/ppoMBPVc7X6jhWPJOuMiLkofyqn+u7lt4Dq8VVRkGs X-Received: by 2002:a5d:9291:: with SMTP id s17mr66456053iom.10.1563831686202; Mon, 22 Jul 2019 14:41:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563831686; cv=none; d=google.com; s=arc-20160816; b=XmcwoFxKnwkkOqQA9CVDbmY0lhOOKQV8tpX8Ow8XAYTX0Y7G+Khky1fnB9xc9XxnmP KVwIEo8PsZ3MeDzXtyaucCaTrYvwb8WKJz3w1cyMQPeH+6vDe6ayUC4UTqZGRDNn6/Ks /r1716XNq/dcuG3wgMgHnHsnCOAlnzakHublor1iO+XNEzD8y8jxEqYtqAuA2/VfpCUG GNlBKZlBBuKgeN3cAkR74d6wsBnHF2b1Srfz5wL6ukoEOgWR5SD3gbmDghAIFKl1K28B Sd1JdEmYo/kEVadUHOyZXR4Jl9Rr9Me1uypLqkwPasAaVG+V7N4gMJpUDCrR2mbGQCQv BM1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=kpFaSmj4IvKUZo5HJUvFkFwAQotFbpEWRO3yuTiKSzM=; b=dKBgAAwsraOArGNI/3cxUIss3LGnexgUWkZe6dUXZ6ovwhSAzTAFMEpIehX18Sz627 jCsDny0NyaurZ1P710dlZIi9fnIBegmkRYjzg70GmzWqyw4DzytKR3egoYZQfjNrj1u4 l7QZnXtPFEz4Dr52pK7XtompX8DBlZ5GU9oO972gzc+NBaK/e4C2O1llF+fQGY9B1UjI +XzAu6Bl3YaGgpKk7X/QHjcjJgUnf9Y6Pgx5ibuWStMLJ5Qe2R53hSQmBLqI6+Pn1OVn ANJtaKL1aMayxefqyoBH8HQmo4Qq8DmnBFSSnWxtnk+yhgjt5U0HOAG0JqKx4Pag9M9e H/5A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p24si52850761iol.54.2019.07.22.14.41.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jul 2019 14:41:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hpg2x-0003IY-19; Mon, 22 Jul 2019 21:40:39 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hpg2r-00036D-Rw for xen-devel@lists.xenproject.org; Mon, 22 Jul 2019 21:40:33 +0000 X-Inumbo-ID: 54aa3c72-acc9-11e9-998a-a3848bc5c860 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 54aa3c72-acc9-11e9-998a-a3848bc5c860; Mon, 22 Jul 2019 21:40:32 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E563E152F; Mon, 22 Jul 2019 14:40:31 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3F5893F71F; Mon, 22 Jul 2019 14:40:31 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 22 Jul 2019 22:39:52 +0100 Message-Id: <20190722213958.5761-30-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190722213958.5761-1-julien.grall@arm.com> References: <20190722213958.5761-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 29/35] xen/arm32: head: Move assembly switch to the runtime PT in secondary CPUs path X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The assembly switch to the runtime PT is only necessary for the secondary CPUs. So move the code in the secondary CPUs path. While this is definitely not compliant with the Arm Arm as we are switching between two differents set of page-tables without turning off the MMU. Turning off the MMU is impossible here as the ID map may clash with other mappings in the runtime page-tables. This will require more rework to avoid the problem. So for now add a TODO in the code. Finally, the code is currently assume that r5 will be properly set to 0 before hand. This is done by create_page_tables() which is called quite early in the boot process. There are a risk this may be oversight in the future and therefore breaking secondary CPUs boot. Instead, set r5 to 0 just before using it. Signed-off-by: Julien Grall --- Changes in v2: - Patch added --- xen/arch/arm/arm32/head.S | 42 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 4081a52dfa..6dc6032498 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -201,6 +201,26 @@ GLOBAL(init_secondary) mov pc, r0 secondary_switched: bl setup_fixmap + + /* + * Non-boot CPUs need to move on to the proper pagetables, which were + * setup in init_secondary_pagetables. + * + * XXX: This is not compliant with the Arm Arm. + */ + ldr r4, =init_ttbr /* VA of HTTBR value stashed by CPU 0 */ + mov r5, #0 + ldrd r4, r5, [r4] /* Actual value */ + dsb + mcrr CP64(r4, r5, HTTBR) + dsb + isb + mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */ + mcr CP32(r0, ICIALLU) /* Flush I-cache */ + mcr CP32(r0, BPIALL) /* Flush branch predictor */ + dsb /* Ensure completion of TLB+BP flush */ + isb + b launch ENDPROC(init_secondary) @@ -504,28 +524,6 @@ ENDPROC(setup_fixmap) launch: PRINT("- Ready -\r\n") - /* The boot CPU should go straight into C now */ - teq r12, #0 - beq 1f - - /* - * Non-boot CPUs need to move on to the proper pagetables, which were - * setup in init_secondary_pagetables. - */ - - ldr r4, =init_ttbr /* VA of HTTBR value stashed by CPU 0 */ - ldrd r4, r5, [r4] /* Actual value */ - dsb - mcrr CP64(r4, r5, HTTBR) - dsb - isb - mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */ - mcr CP32(r0, ICIALLU) /* Flush I-cache */ - mcr CP32(r0, BPIALL) /* Flush branch predictor */ - dsb /* Ensure completion of TLB+BP flush */ - isb - -1: ldr r0, =init_data add r0, #INITINFO_stack /* Find the boot-time stack */ ldr sp, [r0]