From patchwork Tue May 14 12:24:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164173 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2554893ili; Tue, 14 May 2019 05:26:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqxYVKkctBFeR80/37tA6/F1hZXw6wzB84BT4CH247HRtI+QjB1LhkRRXt0PfndH111vnHzb X-Received: by 2002:a24:64d0:: with SMTP id t199mr3236577itc.136.1557836763207; Tue, 14 May 2019 05:26:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836763; cv=none; d=google.com; s=arc-20160816; b=NK/JW9fkVUvZ5sLocmayfCarEMJ3h19EeHBEICaZ5uBVG+9CaiO63gOVKR1ziyfVRV NRgPRnBMakaI641s4L7ohu5ex398OUSIp1A3Nu6xEMc0X4BN4aWoe/ryQpbRvgQornYd uHKYhS6z74BqC8BYDifkEnAOO7JmTydD5NHcJ5rMSWO1fSIECWFQ/xbPeRBmTXNyc0ie oqmI0QNupoKNI/kXgb7AraCIblSH2fWxOM8wjmgKE4iINGRLDuTB3qpkfi10H/i8SMGE rqqx8Uh6siylNN2rk9k4MrhDdtdsyaysxMt/RPfenOBfotjJcX2/HohBoW6vH6uzgO9A 0vaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=NhttHYK9axvC7NjxS3V0NWoO4LbqN2kE343kaONEYDY=; b=bJR3kA3RfLOlCPhglcLGcbkdFfwPC/8vh61kQxiHagI0FlA9rPiFrQpihSD0v+2//E eH1jzeoVOio4WhfG+2rNb0wbIa/bIH38kuubH6dcHqRavMOOaljwxwUWhbnQc7tAk30A JYQiBZ0r8KF1MXJj9CT55rqdPNsgsUEX0Q6UXMUm1fu2GTs6HGKhuqgFLtxJ+gaCJfdy lc8GnQfwwra2egvSS2SqSyKXxheIkxBvQAU3lzyJpBtCkN5h4icAHcjXFdAIrIcFcAMO fVKJEPnYkgZvvrMf9X4ZVE/Nnrwd+f+zkleUhgh4wxAbWMXXgLZdI/BRCDqWb9XQ+RYc V5zw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id u12si10048803jao.13.2019.05.14.05.26.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:26:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWUY-0002Wi-RP; Tue, 14 May 2019 12:25:10 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWUY-0002W9-CG for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:25:10 +0000 X-Inumbo-ID: 501f8604-7643-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 501f8604-7643-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:25:09 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EEA0915AB; Tue, 14 May 2019 05:25:08 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DF2483F71E; Tue, 14 May 2019 05:25:07 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:24:41 +0100 Message-Id: <20190514122456.28559-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122456.28559-1-julien.grall@arm.com> References: <20190514122456.28559-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 RESEND v2 04/19] xen/arm: Rework HSCTLR_BASE X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The current value of HSCTLR_BASE for Arm64 is pretty wrong. It would actually turn on SCTLR_EL2.nAA (bit 6) on hardware implementing ARMv8.4-LSE. Furthermore, the documentation of what is cleared/set in SCTLR_EL2 is also not correct and looks like to be a verbatim copy from Arm32. HSCTLR_BASE is replaced with a bunch of per-architecture new defines helping to understand better what is the initialie value for SCTLR_EL2/HSCTLR. Note the defines *_CLEAR are only used to check the state of each bits are known. Lastly, the documentation is dropped from arm{32,64}/head.S as it would be pretty easy to get out-of-sync with the definitions. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Use BIT(..., UL) instead of _BITUL --- xen/arch/arm/arm32/head.S | 12 +-------- xen/arch/arm/arm64/head.S | 10 +------- xen/include/asm-arm/processor.h | 54 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 55 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 454d24537c..8a98607459 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -234,17 +234,7 @@ cpu_init_done: ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) mcr CP32(r0, HTCR) - /* - * Set up the HSCTLR: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking enabled, - * MMU translation disabled (for now). - */ - ldr r0, =(HSCTLR_BASE|SCTLR_Axx_ELx_A) + ldr r0, =HSCTLR_SET mcr CP32(r0, HSCTLR) /* diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 8a6be3352e..4fe904c51d 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -363,15 +363,7 @@ skip_bss: msr tcr_el2, x0 - /* Set up the SCTLR_EL2: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking disabled, - * MMU translation disabled (for now). */ - ldr x0, =(HSCTLR_BASE) + ldr x0, =SCTLR_EL2_SET msr SCTLR_EL2, x0 /* Ensure that any exceptions encountered at EL2 diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index bbcba061ca..9afc3786c5 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -127,6 +127,9 @@ #define SCTLR_A32_ELx_TE BIT(30, UL) #define SCTLR_A32_ELx_FI BIT(21, UL) +/* Common bits for SCTLR_ELx for Arm64 */ +#define SCTLR_A64_ELx_SA BIT(3, UL) + /* Common bits for SCTLR_ELx on all architectures */ #define SCTLR_Axx_ELx_EE BIT(25, UL) #define SCTLR_Axx_ELx_WXN BIT(19, UL) @@ -135,7 +138,56 @@ #define SCTLR_Axx_ELx_A BIT(1, UL) #define SCTLR_Axx_ELx_M BIT(0, UL) -#define HSCTLR_BASE _AC(0x30c51878,U) +#ifdef CONFIG_ARM_32 + +#define HSCTLR_RES1 (BIT( 3, UL) | BIT( 4, UL) | BIT( 5, UL) |\ + BIT( 6, UL) | BIT(11, UL) | BIT(16, UL) |\ + BIT(18, UL) | BIT(22, UL) | BIT(23, UL) |\ + BIT(28, UL) | BIT(29, UL)) + +#define HSCTLR_RES0 (BIT(7, UL) | BIT(8, UL) | BIT(9, UL) | BIT(10, UL) |\ + BIT(13, UL) | BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\ + BIT(20, UL) | BIT(24, UL) | BIT(26, UL) | BIT(27, UL) |\ + BIT(31, UL)) + +/* Initial value for HSCTLR */ +#define HSCTLR_SET (HSCTLR_RES1 | SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_I) + +#define HSCTLR_CLEAR (HSCTLR_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_WXN |\ + SCTLR_A32_ELx_FI | SCTLR_Axx_ELx_EE |\ + SCTLR_A32_ELx_TE) + +#if (HSCTLR_SET ^ HSCTLR_CLEAR) != 0xffffffffU +#error "Inconsistent HSCTLR set/clear bits" +#endif + +#else + +#define SCTLR_EL2_RES1 (BIT( 4, UL) | BIT( 5, UL) | BIT(11, UL) |\ + BIT(16, UL) | BIT(18, UL) | BIT(22, UL) |\ + BIT(23, UL) | BIT(28, UL) | BIT(29, UL)) + +#define SCTLR_EL2_RES0 (BIT( 6, UL) | BIT( 7, UL) | BIT( 8, UL) |\ + BIT( 9, UL) | BIT(10, UL) | BIT(13, UL) |\ + BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\ + BIT(20, UL) | BIT(21, UL) | BIT(24, UL) |\ + BIT(26, UL) | BIT(27, UL) | BIT(30, UL) |\ + BIT(31, UL) | (0xffffffffULL << 32)) + +/* Initial value for SCTLR_EL2 */ +#define SCTLR_EL2_SET (SCTLR_EL2_RES1 | SCTLR_A64_ELx_SA |\ + SCTLR_Axx_ELx_I) + +#define SCTLR_EL2_CLEAR (SCTLR_EL2_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_C |\ + SCTLR_Axx_ELx_WXN | SCTLR_Axx_ELx_EE) + +#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL +#error "Inconsistent SCTLR_EL2 set/clear bits" +#endif + +#endif /* HCR Hyp Configuration Register */ #define HCR_RW (_AC(1,UL)<<31) /* Register Width, ARM64 only */