From patchwork Tue Dec 18 18:04:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 154172 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4015000ljp; Tue, 18 Dec 2018 10:06:24 -0800 (PST) X-Google-Smtp-Source: AFSGD/WrMRgzkKqca3wwu9U21bqiQAx+Wc2K0PiieMqH34W6YMSZZleG0YTndaWjUUetDglSgeUd X-Received: by 2002:ac8:7094:: with SMTP id y20mr556929qto.380.1545156384362; Tue, 18 Dec 2018 10:06:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545156384; cv=none; d=google.com; s=arc-20160816; b=vVRv6A9c6i58d5jWl1ZAtOQPXq4/CSqK4ZoZ1dMe7i1CLyXVrfsX9vDPdykSYoOfY3 B3vcgTR9WgQVz6LikrgkP+9tra03Q8ofad3MmBbd63nfNjBfFL3E6E9zWN6rU6SmQY84 uMO+qnHrijBPKf6qhjBct8ekOg1ib0VG/N/Gh7ra9Z9f5zT7f+qc8iW+4U5EFN5fAa4b /F4EnB7QZ0uTN8jZ0UsULP/EtqtUgXv6Z+JU9mAkJ8G1U7mw6fh9iUbmFHWO5TZqUuTO bhamBkJ4VZu2ig2Nbsq5e+AR/exgoZ8U+kDxAs1UZKyCmyFGNQdC8kLelOq6zdpecf9f swfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=OmRC+QzqWUNOKjVSiqzE7yl8Kf4qC35nmjYIjz6E3Mw=; b=aV1kjRvpKzIQs43InaNBp5QS58wXFbj5BnI7o/mbF85Q/bW6WeG2Zj5k7QRAIYU1yG sTvw0EUlqncxUPh6/sApz7m1S10lOvgwQWrzOEB3e1yb2D/3aQzB/krHpd88/4Prtew8 5Ex/yLvT+pvN5Zf6Bu4Veefl5ioPesCOLwymaSW48rpMLBccMmzjTSS9+8ry0tVxmMpo ZizmQhRb3ps5NoDd+hd2v5zVibgTdNshRfzQ870Xuo5kn97oL562B1LX3WVVGIrX5mW6 +w9PDbsxqmvsbaBGhVf/oTgGQCB9yFmqCDfAZ5HrbbB0vaEH42nIWxAhFfXVbl3Lp6JD WfFQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id x3si401521qtd.345.2018.12.18.10.06.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 10:06:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gZJjI-0006am-WF; Tue, 18 Dec 2018 18:04:29 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gZJjI-0006ac-Iq for xen-devel@lists.xenproject.org; Tue, 18 Dec 2018 18:04:28 +0000 X-Inumbo-ID: 5bc696d8-02ef-11e9-9e66-b35f198798f0 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 5bc696d8-02ef-11e9-9e66-b35f198798f0; Tue, 18 Dec 2018 18:04:27 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AE3331650; Tue, 18 Dec 2018 10:04:26 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E30183F5C0; Tue, 18 Dec 2018 10:04:25 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 18 Dec 2018 18:04:15 +0000 Message-Id: <20181218180417.22134-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181218180417.22134-1-julien.grall@arm.com> References: <20181218180417.22134-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH for-4.12 v4 2/4] xen/arm: vsysreg: Add wrapper to handle sysreg access trapped by HCR_EL2.TVM X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will require to emulate some accesses to system registers trapped by HCR_EL2.TVM. When set, all NS EL1 writes to the virtual memory control registers will be trapped to the hypervisor. This patch adds the infrastructure to passthrough the access to the host registers. Note that HCR_EL2.TVM will be set in a follow-up patch dynamically. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v4: - Add Stefano's reviewed by Changes in v2: - Add missing include vreg.h - Update documentation reference to the lastest one --- xen/arch/arm/arm64/vsysreg.c | 58 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 6e60824572..16ac9c344a 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -21,8 +21,49 @@ #include #include #include +#include #include +/* + * Macro to help generating helpers for registers trapped when + * HCR_EL2.TVM is set. + * + * Note that it only traps NS write access from EL1. + */ +#define TVM_REG(reg) \ +static bool vreg_emulate_##reg(struct cpu_user_regs *regs, \ + uint64_t *r, bool read) \ +{ \ + GUEST_BUG_ON(read); \ + WRITE_SYSREG64(*r, reg); \ + \ + return true; \ +} + +/* Defining helpers for emulating sysreg registers. */ +TVM_REG(SCTLR_EL1) +TVM_REG(TTBR0_EL1) +TVM_REG(TTBR1_EL1) +TVM_REG(TCR_EL1) +TVM_REG(ESR_EL1) +TVM_REG(FAR_EL1) +TVM_REG(AFSR0_EL1) +TVM_REG(AFSR1_EL1) +TVM_REG(MAIR_EL1) +TVM_REG(AMAIR_EL1) +TVM_REG(CONTEXTIDR_EL1) + +/* Macro to generate easily case for co-processor emulation */ +#define GENERATE_CASE(reg) \ + case HSR_SYSREG_##reg: \ + { \ + bool res; \ + \ + res = vreg_emulate_sysreg64(regs, hsr, vreg_emulate_##reg); \ + ASSERT(res); \ + break; \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -44,6 +85,23 @@ void do_sysreg(struct cpu_user_regs *regs, break; /* + * HCR_EL2.TVM + * + * ARMv8 (DDI 0487D.a): Table D1-38 + */ + GENERATE_CASE(SCTLR_EL1) + GENERATE_CASE(TTBR0_EL1) + GENERATE_CASE(TTBR1_EL1) + GENERATE_CASE(TCR_EL1) + GENERATE_CASE(ESR_EL1) + GENERATE_CASE(FAR_EL1) + GENERATE_CASE(AFSR0_EL1) + GENERATE_CASE(AFSR1_EL1) + GENERATE_CASE(MAIR_EL1) + GENERATE_CASE(AMAIR_EL1) + GENERATE_CASE(CONTEXTIDR_EL1) + + /* * MDCR_EL2.TDRA * * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57