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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id w125sm3217102wmw.20.2018.03.15.13.31.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Mar 2018 13:31:51 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 15 Mar 2018 20:30:46 +0000 Message-Id: <20180315203050.19791-42-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180315203050.19791-1-andre.przywara@linaro.org> References: <20180315203050.19791-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 41/45] ARM: new VGIC: Add vgic_v2_enable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Enable the VGIC operation by properly initialising the registers in the hypervisor GIC interface. This is based on Linux commit f7b6985cc3d0, written by Eric Auger. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog v1 ... v2: - move patch from later part in the series xen/arch/arm/vgic/vgic-v2.c | 6 ++++++ xen/arch/arm/vgic/vgic.h | 1 + 2 files changed, 7 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c index bc5c7895f4..4662346327 100644 --- a/xen/arch/arm/vgic/vgic-v2.c +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -219,6 +219,12 @@ void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) gic_hw_ops->write_lr(lr, &lr_val); } +void vgic_v2_enable(struct vcpu *vcpu) +{ + /* Get the show on the road... */ + gic_hw_ops->update_hcr_status(GICH_HCR_EN, 1); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index deefbb3ef7..def1ac478a 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -62,6 +62,7 @@ void vgic_sync_hardware_irq(struct domain *d, void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); +void vgic_v2_enable(struct vcpu *vcpu); int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn, enum vgic_type);