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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id w125sm3217102wmw.20.2018.03.15.13.31.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Mar 2018 13:31:49 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 15 Mar 2018 20:30:45 +0000 Message-Id: <20180315203050.19791-41-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180315203050.19791-1-andre.przywara@linaro.org> References: <20180315203050.19791-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 40/45] ARM: new VGIC: vgic-init: register VGIC X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This patch implements the function which is called by Xen when it wants to register the virtual GIC. This also implements vgic_max_vcpus() for the new VGIC, which reports back the maximum number of VCPUs a certain GIC model supports. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-init.c | 60 +++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.c | 22 ++++++++++++++++ xen/arch/arm/vgic/vgic.h | 3 +++ 3 files changed, 85 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-init.c diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c new file mode 100644 index 0000000000..d091c92ed0 --- /dev/null +++ b/xen/arch/arm/vgic/vgic-init.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include "vgic.h" + +/* CREATION */ + +/** + * domain_vgic_register: create a virtual GIC + * @d: domain pointer + * @mmio_count: pointer to add number of required MMIO regions + * + * was: kvm_vgic_create + */ +int domain_vgic_register(struct domain *d, int *mmio_count) +{ + switch ( d->arch.vgic.version ) + { + case GIC_V2: + *mmio_count = 1; + break; + default: + BUG(); + } + + if ( d->max_vcpus > domain_max_vcpus(d) ) + return -E2BIG; + + d->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; + d->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; + d->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; + + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 002fec57e6..4b9664f313 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -946,6 +946,28 @@ void vgic_sync_hardware_irq(struct domain *d, spin_unlock_irqrestore(&desc->lock, flags); } +unsigned int vgic_max_vcpus(const struct domain *d) +{ + unsigned int vgic_vcpu_limit; + + switch ( d->arch.vgic.version ) + { +#ifdef CONFIG_HAS_GICV3 + case GIC_V3: + vgic_vcpu_limit = VGIC_V3_MAX_CPUS; + break; +#endif + case GIC_V2: + vgic_vcpu_limit = VGIC_V2_MAX_CPUS; + break; + default: + vgic_vcpu_limit = MAX_VIRT_CPUS; + break; + } + + return min_t(unsigned int, MAX_VIRT_CPUS, vgic_vcpu_limit); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 2feed9615f..deefbb3ef7 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -21,6 +21,9 @@ #define VARIANT_ID_XEN 0x01 #define IMPLEMENTER_ARM 0x43b +#define VGIC_ADDR_UNDEF INVALID_PADDR +#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) + #define VGIC_PRI_BITS 5 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)