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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id w125sm3217102wmw.20.2018.03.15.13.31.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Mar 2018 13:31:42 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 15 Mar 2018 20:30:38 +0000 Message-Id: <20180315203050.19791-34-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180315203050.19791-1-andre.przywara@linaro.org> References: <20180315203050.19791-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 33/45] ARM: new VGIC: Handle hardware mapped IRQs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The VGIC supports virtual IRQs to be connected to a hardware IRQ, so when a guest EOIs the virtual interrupt, it affects the state of that corresponding interrupt on the hardware side at the same time. Implement the interface that the Xen arch/core code expects to connect the virtual and the physical world. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog v1 ... v2: - Add Reviewed-by: xen/arch/arm/vgic/vgic.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 963d5e5f6e..7ff680443c 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -689,6 +689,77 @@ void vgic_kick_vcpus(struct domain *d) } } +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq) +{ + struct irq_desc *desc = NULL; + struct vgic_irq *irq = vgic_get_irq(d, v, virq); + unsigned long flags; + + if ( !irq ) + return NULL; + + spin_lock_irqsave(&irq->irq_lock, flags); + if ( irq->hw ) + { + ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS); + desc = irq_to_desc(irq->hwintid); + } + spin_unlock_irqrestore(&irq->irq_lock, flags); + + vgic_put_irq(d, irq); + + return desc; +} + +/* + * was: + * int kvm_vgic_map_phys_irq(struct vcpu *vcpu, u32 virt_irq, u32 phys_irq) + * int kvm_vgic_unmap_phys_irq(struct vcpu *vcpu, unsigned int virt_irq) + */ +int vgic_connect_hw_irq(struct domain *d, struct vcpu *vcpu, + unsigned int virt_irq, struct irq_desc *desc, + bool connect) +{ + struct vgic_irq *irq = vgic_get_irq(d, vcpu, virt_irq); + unsigned long flags; + int ret = 0; + + if ( !irq ) + return -EINVAL; + + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( connect ) /* assign a mapped IRQ */ + { + /* The VIRQ should not be already enabled by the guest */ + if ( !irq->hw && !irq->enabled ) + { + irq->hw = true; + irq->hwintid = desc->irq; + } + else + ret = -EBUSY; + } + else /* remove a mapped IRQ */ + { + if ( desc && irq->hwintid != desc->irq ) + { + ret = -EINVAL; + } + else + { + irq->hw = false; + irq->hwintid = 0; + } + } + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(d, irq); + + return ret; +} + static unsigned int translate_irq_type(bool is_level) { return is_level ? IRQ_TYPE_LEVEL_HIGH : IRQ_TYPE_EDGE_RISING;