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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:29 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:25 +0000 Message-Id: <20180305160415.16760-8-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 07/57] ARM: VGIC: rename gic_inject() and gic_clear_lrs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The two central functions to synchronise our emulated VGIC state with the GIC hardware (the LRs, really), are named somewhat confusingly. Rename them from gic_inject() to vgic_sync_to_lrs() and from gic_clear_lrs() to vgic_sync_from_lrs(), to make the code more readable. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-vgic.c | 4 ++-- xen/arch/arm/traps.c | 4 ++-- xen/include/asm-arm/gic.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index d273863556..c0fe38fd37 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -247,7 +247,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) } } -void gic_clear_lrs(struct vcpu *v) +void vgic_sync_from_lrs(struct vcpu *v) { int i = 0; unsigned long flags; @@ -377,7 +377,7 @@ out: return rc; } -void gic_inject(void) +void vgic_sync_to_lrs(void) { ASSERT(!local_irq_is_enabled()); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1cba7e584d..7411bff7a7 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2024,7 +2024,7 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) if ( current->arch.hcr_el2 & HCR_VA ) current->arch.hcr_el2 = READ_SYSREG(HCR_EL2); - gic_clear_lrs(current); + vgic_sync_from_lrs(current); } } @@ -2234,7 +2234,7 @@ void leave_hypervisor_tail(void) { local_irq_disable(); if (!softirq_pending(smp_processor_id())) { - gic_inject(); + vgic_sync_to_lrs(); /* * If the SErrors handle option is "DIVERSE", we have to prevent diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 497f195bc1..e2ae4254ed 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -237,7 +237,7 @@ extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, struct irq_desc *desc); -extern void gic_inject(void); +extern void vgic_sync_to_lrs(void); extern void gic_clear_pending_irqs(struct vcpu *v); extern int gic_events_need_delivery(void); @@ -295,7 +295,7 @@ extern unsigned int gic_number_lines(void); /* IRQ translation function for the device tree */ int gic_irq_xlate(const u32 *intspec, unsigned int intsize, unsigned int *out_hwirq, unsigned int *out_type); -void gic_clear_lrs(struct vcpu *v); +void vgic_sync_from_lrs(struct vcpu *v); struct gic_info { /* GIC version */