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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:12 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:07 +0000 Message-Id: <20180305160415.16760-50-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 49/57] ARM: new VGIC: provide system register emulation stub X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Xen arch code traps system registers writes from the guest and will relay anything GIC related to the VGIC. Since this affects only GICv3 (which we don't yet emulate), provide a stub implementation of vgic_emulate() for now. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - no changes xen/arch/arm/vgic/vgic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 2a2b8fd1eb..e1952c872d 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -813,6 +813,13 @@ struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, return desc; } +bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr) +{ + ASSERT(current->domain->arch.vgic.version == GIC_V3); + + return false; +} + /* * was: * int kvm_vgic_map_phys_irq(struct vcpu *vcpu, u32 virt_irq, u32 phys_irq)