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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:26 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:22 +0000 Message-Id: <20180305160415.16760-5-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 04/57] ARM: GICv3: simplify GICv3 redistributor stride handling X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Instead of hard coding the architected redistributor stride into the code, lets use a clear #define to the two values for GICv3 and GICv4 and clarify the algorithm to determine the needed stride value. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - no changes xen/arch/arm/gic-v3.c | 18 ++++++++++-------- xen/include/asm-arm/gic_v3_defs.h | 5 +++++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index b1f8a86409..be1787b39a 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -690,6 +690,15 @@ static int __init gicv3_populate_rdist(void) do { typer = readq_relaxed(ptr + GICR_TYPER); + /* Set the architectural redist size if not overridden by DT. */ + if ( !gicv3.rdist_stride ) + { + if ( typer & GICR_TYPER_VLPIS ) + gicv3.rdist_stride = GICV4_GICR_SIZE; + else + gicv3.rdist_stride = GICV3_GICR_SIZE; + } + if ( (typer >> 32) == aff ) { this_cpu(rbase) = ptr; @@ -732,14 +741,7 @@ static int __init gicv3_populate_rdist(void) if ( gicv3.rdist_regions[i].single_rdist ) break; - if ( gicv3.rdist_stride ) - ptr += gicv3.rdist_stride; - else - { - ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ - if ( typer & GICR_TYPER_VLPIS ) - ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ - } + ptr += gicv3.rdist_stride; } while ( !(typer & GICR_TYPER_LAST) ); } diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 65c9dc47cf..412e41afed 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -18,6 +18,8 @@ #ifndef __ASM_ARM_GIC_V3_DEFS_H__ #define __ASM_ARM_GIC_V3_DEFS_H__ +#include + /* * Additional registers defined in GIC v3. * Common GICD registers are defined in gic.h @@ -68,6 +70,9 @@ #define GICV3_GICD_IIDR_VAL 0x34c #define GICV3_GICR_IIDR_VAL GICV3_GICD_IIDR_VAL +#define GICV3_GICR_SIZE (2 * SZ_64K) +#define GICV4_GICR_SIZE (4 * SZ_64K) + #define GICR_CTLR (0x0000) #define GICR_IIDR (0x0004) #define GICR_TYPER (0x0008)