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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:10 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:05 +0000 Message-Id: <20180305160415.16760-48-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 47/57] ARM: new VGIC: Handle virtual IRQ allocation/reservation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To find an unused virtual IRQ number Xen uses a scheme to track used virtual IRQs. Implement this interface in the new VGIC to make the Xen core/arch code happy. This is actually somewhat VGIC agnostic, so is mostly a copy of the code from the old VGIC. But it has to live in the VGIC files, so we can't easily reuse the existing implementation. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - no changes xen/arch/arm/vgic/vgic.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 0bf257c865..e9ef992e1e 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -721,6 +721,50 @@ bool vgic_evtchn_irq_pending(struct vcpu *v) return pending; } +bool vgic_reserve_virq(struct domain *d, unsigned int virq) +{ + if ( virq >= vgic_num_irqs(d) ) + return false; + + return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs); +} + +int vgic_allocate_virq(struct domain *d, bool spi) +{ + int first, end; + unsigned int virq; + + if ( !spi ) + { + /* We only allocate PPIs. SGIs are all reserved */ + first = 16; + end = 32; + } + else + { + first = 32; + end = vgic_num_irqs(d); + } + + /* + * There is no spinlock to protect allocated_irqs, therefore + * test_and_set_bit may fail. If so retry it. + */ + do + { + virq = find_next_zero_bit(d->arch.vgic.allocated_irqs, end, first); + if ( virq >= end ) + return -1; + } while ( test_and_set_bit(virq, d->arch.vgic.allocated_irqs) ); + + return virq; +} + +void vgic_free_virq(struct domain *d, unsigned int virq) +{ + clear_bit(virq, d->arch.vgic.allocated_irqs); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) {