| Message ID | 20180305160415.16760-42-andre.przywara@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | New VGIC(-v2) implementation | expand |
Hi Andre, On 05/03/18 16:03, Andre Przywara wrote: > The config register handlers are shared between the v2 and v3 emulation, > so their implementation goes into vgic-mmio.c, to be easily referenced > from the v3 emulation as well later. > > This is based on Linux commit 79717e4ac09c, written by Andre Przywara. > > Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Reviewed-by: Julien Grall <julien.grall@arm.com> Cheers, > --- > Changelog RFC ... v1: > - use C99 data types > > xen/arch/arm/vgic/vgic-mmio-v2.c | 2 +- > xen/arch/arm/vgic/vgic-mmio.c | 54 ++++++++++++++++++++++++++++++++++++++++ > xen/arch/arm/vgic/vgic-mmio.h | 7 ++++++ > 3 files changed, 62 insertions(+), 1 deletion(-) > > diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c > index 29db9dec6f..d19ddd3f1e 100644 > --- a/xen/arch/arm/vgic/vgic-mmio-v2.c > +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c > @@ -104,7 +104,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { > vgic_mmio_read_raz, vgic_mmio_write_wi, 8, > VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), > REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, > - vgic_mmio_read_raz, vgic_mmio_write_wi, 2, > + vgic_mmio_read_config, vgic_mmio_write_config, 2, > VGIC_ACCESS_32bit), > REGISTER_DESC_WITH_LENGTH(GICD_SGIR, > vgic_mmio_read_raz, vgic_mmio_write_wi, 4, > diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c > index 538f08bc66..31f7cf706b 100644 > --- a/xen/arch/arm/vgic/vgic-mmio.c > +++ b/xen/arch/arm/vgic/vgic-mmio.c > @@ -431,6 +431,60 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, > } > } > > +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, > + paddr_t addr, unsigned int len) > +{ > + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 2); > + uint32_t value = 0; > + int i; > + > + for ( i = 0; i < len * 4; i++ ) > + { > + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); > + > + if ( irq->config == VGIC_CONFIG_EDGE ) > + value |= (2U << (i * 2)); > + > + vgic_put_irq(vcpu->domain, irq); > + } > + > + return value; > +} > + > +void vgic_mmio_write_config(struct vcpu *vcpu, > + paddr_t addr, unsigned int len, > + unsigned long val) > +{ > + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 2); > + int i; > + unsigned long flags; > + > + for ( i = 0; i < len * 4; i++ ) > + { > + struct vgic_irq *irq; > + > + /* > + * The configuration cannot be changed for SGIs in general, > + * for PPIs this is IMPLEMENTATION DEFINED. The arch timer > + * code relies on PPIs being level triggered, so we also > + * make them read-only here. > + */ > + if ( intid + i < VGIC_NR_PRIVATE_IRQS ) > + continue; > + > + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); > + spin_lock_irqsave(&irq->irq_lock, flags); > + > + if ( test_bit(i * 2 + 1, &val) ) > + irq->config = VGIC_CONFIG_EDGE; > + else > + irq->config = VGIC_CONFIG_LEVEL; > + > + spin_unlock_irqrestore(&irq->irq_lock, flags); > + vgic_put_irq(vcpu->domain, irq); > + } > +} > + > static int match_region(const void *key, const void *elt) > { > const unsigned int offset = (unsigned long)key; > diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h > index e3f9029344..bbf0d181ae 100644 > --- a/xen/arch/arm/vgic/vgic-mmio.h > +++ b/xen/arch/arm/vgic/vgic-mmio.h > @@ -136,6 +136,13 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, > paddr_t addr, unsigned int len, > unsigned long val); > > +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, > + paddr_t addr, unsigned int len); > + > +void vgic_mmio_write_config(struct vcpu *vcpu, > + paddr_t addr, unsigned int len, > + unsigned long val); > + > unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); > > #endif >
diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 29db9dec6f..d19ddd3f1e 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -104,7 +104,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_raz, vgic_mmio_write_wi, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 2, + vgic_mmio_read_config, vgic_mmio_write_config, 2, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_SGIR, vgic_mmio_read_raz, vgic_mmio_write_wi, 4, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 538f08bc66..31f7cf706b 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -431,6 +431,60 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 2); + uint32_t value = 0; + int i; + + for ( i = 0; i < len * 4; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->config == VGIC_CONFIG_EDGE ) + value |= (2U << (i * 2)); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +void vgic_mmio_write_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 2); + int i; + unsigned long flags; + + for ( i = 0; i < len * 4; i++ ) + { + struct vgic_irq *irq; + + /* + * The configuration cannot be changed for SGIs in general, + * for PPIs this is IMPLEMENTATION DEFINED. The arch timer + * code relies on PPIs being level triggered, so we also + * make them read-only here. + */ + if ( intid + i < VGIC_NR_PRIVATE_IRQS ) + continue; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( test_bit(i * 2 + 1, &val) ) + irq->config = VGIC_CONFIG_EDGE; + else + irq->config = VGIC_CONFIG_LEVEL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index e3f9029344..bbf0d181ae 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -136,6 +136,13 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif
The config register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. This is based on Linux commit 79717e4ac09c, written by Andre Przywara. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> --- Changelog RFC ... v1: - use C99 data types xen/arch/arm/vgic/vgic-mmio-v2.c | 2 +- xen/arch/arm/vgic/vgic-mmio.c | 54 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 7 ++++++ 3 files changed, 62 insertions(+), 1 deletion(-)