From patchwork Mon Mar 5 16:03:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130677 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853871lja; Mon, 5 Mar 2018 08:07:14 -0800 (PST) X-Google-Smtp-Source: AG47ELtLanv1i5D8yDZXU0IbjV1byyymGxOgbrykJ139Rf3E9uqWB1NCjqS/s++V+lSKKc5uA+rf X-Received: by 10.36.43.137 with SMTP id h131mr8914526ita.97.1520266034326; Mon, 05 Mar 2018 08:07:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266034; cv=none; d=google.com; s=arc-20160816; b=c+YQHPl1lGO+lKXle7vFT9ijFfIZViez9anLoNYU/xdykien9I0K4tkpriKi/KZQ6/ tYf1h18JcdXq6zV7jXYvM0UukvHaP6WF6vtBaBjxviGaLnxL9F3tCaEcUpPhsVkAPEyy /onSZ6tLsckUJlbRIQv/evDAxs0Nmp2+quP9aiEB3eGWLnt1uaKIX3xx1vxMwaBIujJC pAJHaXGfU6s6DX8J6PamXRt9pebuWjvFidzi+xoxnLLQkMi0iMJrIpuUpqNBYqX0YgSf lPyi4Vdj4yDsmUkHcOJILpi6iHnH7crRvz/WQza3zkuwn3PESLqU1RO6nY53EsFVBmvG 1uCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=rwM9ZyfizDQkJ3T7Td9W2flX9BbTMeRXb18LpVppKAM=; b=QFaGvLGM7TcLNBnWCXsLlTH2BXEzL2oAxz9zaorVyZYN8Qo4CHJSS6GfVxHbLIa9Rw 1FwmnKwDoiYv3tfdDgaEwSLiLezt5vi2wltoZcG/r7U2OS5SwbCu+mN74bPSYSSC4ge7 yqcYrN5mwVCLpktvKqm2nMih5ZFd7jgyDT/NB2S4HvVLnzVHPpdU+/pFTtgU07B76EoH llpGWbvyE5uLG+0tjMXNW8ubxS++mNoKlJIBrmzP+t9kY1ex47DEd8CPyhB4ycFBxLF+ s4MzcYLJcUS2y1Ya+YTtTz9PS3c9U6e1g91b52/ccrYY2qmsGOSAedLP7su0z1ufRC59 JNLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=A5HMpZjt; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d26si8692995iob.50.2018.03.05.08.07.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 08:07:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=A5HMpZjt; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbQ-0007MN-Py; Mon, 05 Mar 2018 16:04:40 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbP-0007KG-7m for xen-devel@lists.xenproject.org; Mon, 05 Mar 2018 16:04:39 +0000 X-Inumbo-ID: c0298b20-208e-11e8-ba59-bc764e045a96 Received: from mail-wm0-x243.google.com (unknown [2a00:1450:400c:c09::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id c0298b20-208e-11e8-ba59-bc764e045a96; Mon, 05 Mar 2018 17:03:32 +0100 (CET) Received: by mail-wm0-x243.google.com with SMTP id 188so16521839wme.1 for ; Mon, 05 Mar 2018 08:04:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IWBSmvfRGf9YfMITgZFyyYblvACQ7sVERHHeSfLViBo=; b=A5HMpZjtNP05A2rp9L70LMKQK3Xp8pKM1KJajiLhfH+boR2rTCYZ0bc5xJDmBaWTLd VxXNub177LD6bivbGkrPoXIm91y25muX9JRSH956tn5BiHLG5xNWb8XiHJCbr6kQIrDk Z9qFDCbaCL2ZSXowwZglmAXvhOomP7vgzjiJ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IWBSmvfRGf9YfMITgZFyyYblvACQ7sVERHHeSfLViBo=; b=HET1/KHT9qYRTqpYaRJkmSKAPQJ/JV3gxIG0YxuPG+vpm63E3aCFPie+bUds6ghRB4 ntTu3vw9ExSGjfGgpXYiVQVDc8obIl50+YdvO5RmHsSN36S9sa4LjNatjjztKzZFUjMq H1ebxT6k9Oz8U3HyLvnp4KYQLp39SbEyK9+oQ9Ib6M4JrneJU1gGj9UsawDwfiNdVDEc ndf6u1THHyLNe6IsI3TV9s9id/Y4ijJ3krpa7M74cQHQ1Raw1mjUMEQyhCNER/MHAfC0 RewAoRqRk4OrcwqNfKwKq/EVFAREcaJj2R0Iufp8YFM6p+T7L3YkyRT1dqlIm09E5ay9 7n3Q== X-Gm-Message-State: AElRT7Gvg3rk3CfkT1MlCwiItUyAI0WJC6xOmF0rmpI8IaFTM0opXp8V WhhxRmIRSyd1X3FRhh0gw7uZbw== X-Received: by 10.28.234.8 with SMTP id i8mr9309495wmh.44.1520265876867; Mon, 05 Mar 2018 08:04:36 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:36 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:32 +0000 Message-Id: <20180305160415.16760-15-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 14/57] ARM: VGIC: Introduce gic_get_nr_lrs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" So far the number of list registers (LRs) a GIC implements is only needed in the hardware facing side of the VGIC code (gic-vgic.c). The new VGIC will need this information in more and multiple places, so export a function that returns the number. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - move gic_get_nr_lrs() into gic.h (as a static inline) xen/arch/arm/gic-vgic.c | 10 +++++----- xen/include/asm-arm/gic.h | 6 ++++++ 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 60c6c463e9..93e42739d9 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -25,7 +25,7 @@ #include #include -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_get_nr_lrs()) - 1)) #undef GIC_DEBUG @@ -110,7 +110,7 @@ static unsigned int gic_find_unused_lr(struct vcpu *v, struct pending_irq *p, unsigned int lr) { - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); struct gic_lr lr_val; @@ -137,7 +137,7 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, unsigned int priority) { int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); struct pending_irq *p = irq_to_pending(v, virtual_irq); ASSERT(spin_is_locked(&v->arch.vgic.lock)); @@ -251,7 +251,7 @@ void vgic_sync_from_lrs(struct vcpu *v) { int i = 0; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); /* The idle domain has no LRs to be cleared. Since gic_restore_state * doesn't write any LR registers for the idle domain they could be @@ -278,7 +278,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) struct pending_irq *p, *t, *p_r; struct list_head *inflight_r; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); int lrs = nr_lrs; spin_lock_irqsave(&v->arch.vgic.lock, flags); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index a23c307c3a..b3f840ea9a 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -374,6 +374,12 @@ struct gic_hw_operations { }; extern const struct gic_hw_operations *gic_hw_ops; + +static inline unsigned int gic_get_nr_lrs(void) +{ + return gic_hw_ops->info->nr_lrs; +} + void register_gic_ops(const struct gic_hw_operations *ops); int gic_make_hwdom_dt_node(const struct domain *d, const struct dt_device_node *gic,