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[209.85.220.65]) by mx.google.com with SMTPS id c2sor7528139pgh.54.2020.04.22.07.35.52 for (Google Transport Security); Wed, 22 Apr 2020 07:35:52 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q8wWVk1c; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EKk8wf3cz8RUWzn1IoJAXdPdtXtapZhuXqAKZvlxhk0=; b=Q8wWVk1ckEkvNGo5uhA1JXDfkNoPrE1CsY1IwOXg92Q4y4AdjWHDV2+/nSZNGB6XTB yrD5WujSF1M0Mz8D0BlZQF1S16h3hTVjLyWqTaT9JlvXZffmX/3vHWYkVbChjJ9Tizd2 iqqPczIw+Kk/UDDdId8MC50u+viNXYq/lGRFNbMEAbLw7fG6gFp1Z5WMK6EGvLQQSCgB PrKLan3ZRMz+C3rjN+QpI//nIShjjPFw1kD1n/MJADcdY+4ydS4DH2LxH3WJmwO+6IaY cO0V+wPMQE9JGH0MGA3Uniy2rCgRrCmDCwORW3VbesffeQ5M/3lCLDOkj/IwLXQJXK5R qnTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EKk8wf3cz8RUWzn1IoJAXdPdtXtapZhuXqAKZvlxhk0=; b=fg9MpD8nadIAfmGcaowQesLH2YGxtxeo4iaBKB2gxFpHMnRANr+LoQntFL1qRg3W9K 68xlBuv9GZvTPl67RFsTH3Qpk9sWVHW0R6amUIf291limBzDIFKfMiy29a43rts6SSZy e3Pyjt9ngkjhVp/e3HHP/SD8XZZ9oOVy2FDtUXCJ9MFqnMnjkw79peD5vdEX4UZnK0zl xK9Cu6ZGDuVLJUVcOZj4IjsJ2MZykS0MR62xhttI16AuTH0lzMGR/9B7sbRNL0XtGFc5 RiO6bSyUkQrROt+5+Dvp/yjkp8QNcksYQ4tkFuaHhQJU3E1cE+ZDe8P4Gc5A1qh/CiSv +IzA== X-Gm-Message-State: AGi0PuZ7ZLwQ69jOiSFKgdHp5v+1NkpS2x2xh7W5BFcIy29bRgkIr/DP 4cgsdXSFl+lyedeqb/j1vCL4XjHN X-Google-Smtp-Source: APiQypIGpdwJVGb3tVlbi4DwamFnWduPC0rVhLqqQD6QG7bYffklXl6F8G0lQOfP67Z2bDs1Al436w== X-Received: by 2002:a63:bf4a:: with SMTP id i10mr27932901pgo.120.1587566151867; Wed, 22 Apr 2020 07:35:51 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([117.252.71.186]) by smtp.gmail.com with ESMTPSA id j13sm5723573pje.1.2020.04.22.07.35.48 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Apr 2020 07:35:50 -0700 (PDT) From: Sumit Garg To: daniel.thompson@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [RFC 1/4] arm64: smp: Introduce a new IPI as IPI_CALL_NMI_FUNC Date: Wed, 22 Apr 2020 20:05:20 +0530 Message-Id: <1587566123-9935-2-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587566123-9935-1-git-send-email-sumit.garg@linaro.org> References: <1587566123-9935-1-git-send-email-sumit.garg@linaro.org> Introduce a new inter processor interrupt as IPI_CALL_NMI_FUNC that can be invoked to run special handlers in NMI context. One such handler example is kgdb_nmicallback() which is invoked in order to round up CPUs to enter kgdb context. As currently pseudo NMIs are supported on specific arm64 platforms which incorporates GICv3 or later version of interrupt controller. In case a particular platform doesn't support pseudo NMIs, IPI_CALL_NMI_FUNC will act as a normal IPI which can still be used to invoke special handlers. Signed-off-by: Sumit Garg --- arch/arm64/include/asm/hardirq.h | 2 +- arch/arm64/include/asm/smp.h | 1 + arch/arm64/kernel/smp.c | 20 +++++++++++++++++++- 3 files changed, 21 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h index 87ad961..abaa23a 100644 --- a/arch/arm64/include/asm/hardirq.h +++ b/arch/arm64/include/asm/hardirq.h @@ -13,7 +13,7 @@ #include #include -#define NR_IPI 7 +#define NR_IPI 8 typedef struct { unsigned int __softirq_pending; diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 40d5ba0..cc32776 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -108,6 +108,7 @@ extern void secondary_entry(void); extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); +extern void arch_send_call_nmi_func_ipi_mask(const struct cpumask *mask); #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 061f60f..42fe7bb 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -74,7 +74,8 @@ enum ipi_msg_type { IPI_CPU_CRASH_STOP, IPI_TIMER, IPI_IRQ_WORK, - IPI_WAKEUP + IPI_WAKEUP, + IPI_CALL_NMI_FUNC }; #ifdef CONFIG_HOTPLUG_CPU @@ -798,6 +799,7 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = { S(IPI_TIMER, "Timer broadcast interrupts"), S(IPI_IRQ_WORK, "IRQ work interrupts"), S(IPI_WAKEUP, "CPU wake-up interrupts"), + S(IPI_CALL_NMI_FUNC, "NMI function call interrupts"), }; static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) @@ -856,6 +858,11 @@ void arch_irq_work_raise(void) } #endif +void arch_send_call_nmi_func_ipi_mask(const struct cpumask *mask) +{ + smp_cross_call(mask, IPI_CALL_NMI_FUNC); +} + static void local_cpu_stop(void) { set_cpu_online(smp_processor_id(), false); @@ -960,6 +967,17 @@ void handle_IPI(int ipinr, struct pt_regs *regs) break; #endif + case IPI_CALL_NMI_FUNC: + /* Handle it as a normal interrupt if not in NMI context */ + if (!in_nmi()) + irq_enter(); + + /* nop, IPI handlers for special features can be added here. */ + + if (!in_nmi()) + irq_exit(); + break; + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break;