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[209.85.220.65]) by mx.google.com with SMTPS id d6sor4318697pfe.71.2018.11.19.22.42.40 for (Google Transport Security); Mon, 19 Nov 2018 22:42:40 -0800 (PST) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G0QEzcJu; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Xx2xszJZxCyI/9/nb2k+6U6ofOWCBfJybDLdeYmZJdI=; b=G0QEzcJuuVRNklfiLtfZUyrl/vVf98WkUn2R4g8GUhaHDDknxDTaIo4bYCybUd/gQu 0tfIpP3Jt59oBmCjXh4oh4/36SZY1TQpV5RSing8pfJe5Q0JxKRtA38YvvrNrRsw7Dob hi0Lvz9iQXbcmGHWNZRjeLjbw0sOnAyQXklWY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Xx2xszJZxCyI/9/nb2k+6U6ofOWCBfJybDLdeYmZJdI=; b=YSZdYqMC3ykw49lHPseYs4sKc8sa9B9tn326UI9kUJARopxoEtYbyLbWqlNeFvPxup rFVa+Mlidod1+QdqB9alPOrMydgG+OFiGf3Lis5C1eWqCtKH3pmYLjAjS07DqvDZmMzm bBG/BnGd3Krg/Ax8+XMUzfKVuIxtYAkNP6NR7FHIfkowPruFX+UaZp7xTYU8yYFiNelA hnTp7M+PYhlOMaZHO5GobLbinrSpg1j9RQhsF50a3mujrDWDEwLwX02/SHwvWVTpweYQ v2MqrrJSzVNPX8i9lW+PPxyWEduNDOJeCGgaPHMVJFbxYY+jH1P7EK5+Pz6X4AgANTXG izgQ== X-Gm-Message-State: AGRZ1gJtr/qvvIOFfIykOnJN8dhEounRD73Car462oHtVm5A+2ySa95A CUxVcxWkpmqozMRlocCjG7uY0U2f X-Google-Smtp-Source: AJdET5eq2TtWigKSmX+9Kc6wpSsGRn1KB1IH3NU8ecYlhxNuGdKAwnucfps+O7Z85JvI6x09dEONzw== X-Received: by 2002:a62:9a09:: with SMTP id o9-v6mr945952pfe.229.1542696160095; Mon, 19 Nov 2018 22:42:40 -0800 (PST) Return-Path: Received: from localhost.localdomain ([117.252.69.224]) by smtp.gmail.com with ESMTPSA id p83sm51534173pfi.85.2018.11.19.22.42.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Nov 2018 22:42:39 -0800 (PST) From: Sumit Garg To: daniel.thompson@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [PATCH v3 2/3] synquacer: Add secure timer interrupt framework Date: Tue, 20 Nov 2018 12:12:15 +0530 Message-Id: <1542696136-5240-2-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542696136-5240-1-git-send-email-sumit.garg@linaro.org> References: <1542696136-5240-1-git-send-email-sumit.garg@linaro.org> Secure timer interrupt is configured to fire every 2ms. Signed-off-by: Sumit Garg --- core/arch/arm/include/arm64.h | 4 +++ core/arch/arm/plat-synquacer/main.c | 30 +++++++++++++++--- core/arch/arm/plat-synquacer/platform_config.h | 2 ++ core/arch/arm/plat-synquacer/sub.mk | 1 + core/arch/arm/plat-synquacer/timer_fiq.c | 43 ++++++++++++++++++++++++++ core/arch/arm/plat-synquacer/timer_fiq.h | 15 +++++++++ 6 files changed, 90 insertions(+), 5 deletions(-) create mode 100644 core/arch/arm/plat-synquacer/timer_fiq.c create mode 100644 core/arch/arm/plat-synquacer/timer_fiq.h -- 2.7.4 diff --git a/core/arch/arm/include/arm64.h b/core/arch/arm/include/arm64.h index 2c1fd8c..0cf14c0 100644 --- a/core/arch/arm/include/arm64.h +++ b/core/arch/arm/include/arm64.h @@ -305,6 +305,10 @@ DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) +DEFINE_REG_READ_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) +DEFINE_REG_WRITE_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1) +DEFINE_REG_READ_FUNC_(cntps_cval, uint32_t, cntps_cval_el1) +DEFINE_REG_WRITE_FUNC_(cntps_cval, uint32_t, cntps_cval_el1) DEFINE_REG_READ_FUNC_(pmccntr, uint64_t, pmccntr_el0) diff --git a/core/arch/arm/plat-synquacer/main.c b/core/arch/arm/plat-synquacer/main.c index c3aac4c..714becd 100644 --- a/core/arch/arm/plat-synquacer/main.c +++ b/core/arch/arm/plat-synquacer/main.c @@ -18,6 +18,7 @@ #include #include #include +#include static void main_fiq(void); @@ -46,7 +47,7 @@ const struct thread_handlers *generic_boot_get_handlers(void) static void main_fiq(void) { - panic(); + gic_it_handle(&gic_data); } void console_init(void) @@ -66,12 +67,31 @@ void main_init_gic(void) if (!gicd_base) panic(); - /* Initialize GIC */ - gic_init(&gic_data, 0, gicd_base); + /* On ARMv8-A, GIC configuration is initialized in TF-A */ + gic_init_base_addr(&gic_data, 0, gicd_base); + itr_init(&gic_data.chip); } -void main_secondary_init_gic(void) +static enum itr_return timer_itr_cb(struct itr_handler *h __unused) +{ + /* Reset timer for next FIQ */ + generic_timer_handler(); + + return ITRR_HANDLED; +} + +static struct itr_handler timer_itr = { + .it = IT_SEC_TIMER, + .flags = ITRF_TRIGGER_LEVEL, + .handler = timer_itr_cb, +}; + +static TEE_Result init_timer_itr(void) { - gic_cpu_init(&gic_data); + itr_add(&timer_itr); + itr_enable(IT_SEC_TIMER); + + return TEE_SUCCESS; } +driver_init(init_timer_itr); diff --git a/core/arch/arm/plat-synquacer/platform_config.h b/core/arch/arm/plat-synquacer/platform_config.h index 4d6d545..f9b1b40 100644 --- a/core/arch/arm/plat-synquacer/platform_config.h +++ b/core/arch/arm/plat-synquacer/platform_config.h @@ -19,6 +19,8 @@ #define CONSOLE_UART_CLK_IN_HZ 62500000 #define CONSOLE_BAUDRATE 115200 +#define IT_SEC_TIMER 29 + #define DRAM0_BASE 0x80000000 /* Platform specific defines */ diff --git a/core/arch/arm/plat-synquacer/sub.mk b/core/arch/arm/plat-synquacer/sub.mk index 8ddc2fd..cfa1dc3 100644 --- a/core/arch/arm/plat-synquacer/sub.mk +++ b/core/arch/arm/plat-synquacer/sub.mk @@ -1,2 +1,3 @@ global-incdirs-y += . srcs-y += main.c +srcs-y += timer_fiq.c diff --git a/core/arch/arm/plat-synquacer/timer_fiq.c b/core/arch/arm/plat-synquacer/timer_fiq.c new file mode 100644 index 0000000..e8395d9 --- /dev/null +++ b/core/arch/arm/plat-synquacer/timer_fiq.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +bool timer_fiq_running = false; + +void generic_timer_start(void) +{ + uint64_t cval; + uint32_t ctl = 1; + + /* The timer will fire every 2 ms */ + cval = read_cntpct() + (read_cntfrq() / 500); + write_cntps_cval(cval); + + /* Enable the secure physical timer */ + write_cntps_ctl(ctl); +} + +void generic_timer_stop(void) +{ + /* Disable the timer */ + write_cntps_ctl(0); +} + +void generic_timer_handler(void) +{ + /* Ensure that the timer did assert the interrupt */ + assert((read_cntps_ctl() >> 2)); + + /* Disable the timer and reprogram it */ + write_cntps_ctl(0); + generic_timer_start(); +} diff --git a/core/arch/arm/plat-synquacer/timer_fiq.h b/core/arch/arm/plat-synquacer/timer_fiq.h new file mode 100644 index 0000000..ebbe5ba --- /dev/null +++ b/core/arch/arm/plat-synquacer/timer_fiq.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (C) 2018, Linaro Limited + */ + +#ifndef __TIMER_FIQ_H +#define __TIMER_FIQ_H + +extern bool timer_fiq_running; + +void generic_timer_start(void); +void generic_timer_stop(void); +void generic_timer_handler(void); + +#endif /* __TIMER_FIQ_H */