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[192.237.175.120]) by mx.google.com with ESMTPS id a82si5857521ita.38.2016.12.07.04.35.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Dec 2016 04:36:00 -0800 (PST) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cEbQN-0006GK-LC; Wed, 07 Dec 2016 12:34:15 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cEbQM-0006EP-4d for xen-devel@lists.xen.org; Wed, 07 Dec 2016 12:34:14 +0000 Received: from [193.109.254.147] by server-2.bemta-6.messagelabs.com id 3B/13-12366-5C108485; Wed, 07 Dec 2016 12:34:13 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTfcQo0e EweluLoslHxezODB6HN39mymAMYo1My8pvyKBNWP91pfMBcu1K16/aWRtYHwo38XIxSEksJlR 4uSs1awQzmlGiaVHXrF0MXJysAloStz5/IkJxBYRkJa49vkyI4jNLOAg8ebjPbAaYQE3iQl7v oDZLAKqEi/n7GTrYuTg4BVwlbi/JREkLCEgJ3Hy2GRWEJsTKHzr61+wciEBF4mvTctYJjByL2 BkWMWoXpxaVJZapGuml1SUmZ5RkpuYmaNraGCml5taXJyYnpqTmFSsl5yfu4kR6F0GINjBOO+ E/yFGSQ4mJVHeXRPcI4T4kvJTKjMSizPii0pzUosPMcpwcChJ8AoDg0VIsCg1PbUiLTMHGGYw aQkOHiUR3n3/gVp5iwsSc4sz0yFSpxgVpcR55zIA9QmAJDJK8+DaYKF9iVFWSpiXEegQIZ6C1 KLczBJU+VeM4hyMSsK8XCBTeDLzSuCmvwJazAS0eN4NsMUliQgpqQbGWetDYpk+H5zpvvWG2O 96litT3j7ecIBz2mW1p4sOM4m8eT0/TbTVanZaM99rR3YhiUM/RIvZbU79OOyjrXyVd8dLAaG Iik+pcqcm5M8tDW6QfCAf9GDlt0OHfrPOvNlg/05cyunO1YfmttKNd/u15Hax2ynMfWZwxcXm oJ30Btud87YLBvsyKrEUZyQaajEXFScCAJt1p6VoAgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-13.tower-27.messagelabs.com!1481114049!66672553!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.0.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 36438 invoked from network); 7 Dec 2016 12:34:09 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-27.messagelabs.com with SMTP; 7 Dec 2016 12:34:09 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 53F6F1570; Wed, 7 Dec 2016 04:34:09 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.218.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B4D5A3F477; Wed, 7 Dec 2016 04:34:08 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 7 Dec 2016 12:33:50 +0000 Message-Id: <1481114033-11024-11-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481114033-11024-1-git-send-email-julien.grall@arm.com> References: <1481114033-11024-1-git-send-email-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 10/13] xen/arm: vreg: Introduce vreg_emulate_cp{32, 64} X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Factorize the code to emulate 32-bit and 64-bit access to a co-processor in specific helpers. The new helpers will be used in different components to simplify the emulation. Finally, the prototypes for the callbacks to emulate 32-bit and 64-bit co-processor access are the same as the sysreg one. Rather than introducing new ones, repurpose the existent prototypes. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/vtimer.c | 37 +++------------------------ xen/include/asm-arm/vreg.h | 64 ++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 62 insertions(+), 39 deletions(-) diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 091b5e7..4ec3b95 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -252,49 +252,28 @@ static bool vtimer_cntp_cval(struct cpu_user_regs *regs, uint64_t *r, static bool vtimer_emulate_cp32(struct cpu_user_regs *regs, union hsr hsr) { struct hsr_cp32 cp32 = hsr.cp32; - /* - * Initialize to zero to avoid leaking data if there is an - * implementation error in the emulation (such as not correctly - * setting r). - */ - uint32_t r = 0; - bool res; - if ( cp32.read ) perfc_incr(vtimer_cp32_reads); else perfc_incr(vtimer_cp32_writes); - if ( !cp32.read ) - r = get_user_reg(regs, cp32.reg); - switch ( hsr.bits & HSR_CP32_REGS_MASK ) { case HSR_CPREG32(CNTP_CTL): - res = vtimer_cntp_ctl(regs, &r, cp32.read); - break; + return vreg_emulate_cp32(regs, hsr, vtimer_cntp_ctl); case HSR_CPREG32(CNTP_TVAL): - res = vtimer_cntp_tval(regs, &r, cp32.read); - break; + return vreg_emulate_cp32(regs, hsr, vtimer_cntp_tval); default: return false; } - - if ( res && cp32.read ) - set_user_reg(regs, cp32.reg, r); - - return res; } static bool vtimer_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr) { struct hsr_cp64 cp64 = hsr.cp64; - uint32_t r1 = get_user_reg(regs, cp64.reg1); - uint32_t r2 = get_user_reg(regs, cp64.reg2); - uint64_t x = (uint64_t)r1 | ((uint64_t)r2 << 32); if ( cp64.read ) perfc_incr(vtimer_cp64_reads); @@ -304,21 +283,11 @@ static bool vtimer_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr) switch ( hsr.bits & HSR_CP64_REGS_MASK ) { case HSR_CPREG64(CNTP_CVAL): - if ( !vtimer_cntp_cval(regs, &x, cp64.read) ) - return false; - break; + return vreg_emulate_cp64(regs, hsr, vtimer_cntp_cval); default: return false; } - - if ( cp64.read ) - { - set_user_reg(regs, cp64.reg1, x & 0xffffffff); - set_user_reg(regs, cp64.reg2, x >> 32); - } - - return true; } #ifdef CONFIG_ARM_64 diff --git a/xen/include/asm-arm/vreg.h b/xen/include/asm-arm/vreg.h index 2671f6e..ed2bd6f 100644 --- a/xen/include/asm-arm/vreg.h +++ b/xen/include/asm-arm/vreg.h @@ -4,14 +4,68 @@ #ifndef __ASM_ARM_VREG__ #define __ASM_ARM_VREG__ -#ifdef CONFIG_ARM_64 -typedef bool (*vreg_sysreg32_fn_t)(struct cpu_user_regs *regs, uint32_t *r, +typedef bool (*vreg_reg32_fn_t)(struct cpu_user_regs *regs, uint32_t *r, bool read); -typedef bool (*vreg_sysreg64_fn_t)(struct cpu_user_regs *regs, uint64_t *r, +typedef bool (*vreg_reg64_fn_t)(struct cpu_user_regs *regs, uint64_t *r, bool read); +static inline bool vreg_emulate_cp32(struct cpu_user_regs *regs, union hsr hsr, + vreg_reg32_fn_t fn) +{ + struct hsr_cp32 cp32 = hsr.cp32; + /* + * Initialize to zero to avoid leaking data if there is an + * implementation error in the emulation (such as not correctly + * setting r). + */ + uint32_t r = 0; + bool ret; + + if ( !cp32.read ) + r = get_user_reg(regs, cp32.reg); + + ret = fn(regs, &r, cp32.read); + + if ( ret && cp32.read ) + set_user_reg(regs, cp32.reg, r); + + return ret; +} + +static inline bool vreg_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr, + vreg_reg64_fn_t fn) +{ + struct hsr_cp64 cp64 = hsr.cp64; + /* + * Initialize to zero to avoid leaking data if there is an + * implementation error in the emulation (such as not correctly + * setting x). + */ + uint64_t x = 0; + bool ret; + + if ( !cp64.read ) + { + uint32_t r1 = get_user_reg(regs, cp64.reg1); + uint32_t r2 = get_user_reg(regs, cp64.reg2); + + x = (uint64_t)r1 | ((uint64_t)r2 << 32); + } + + ret = fn(regs, &x, cp64.read); + + if ( ret && cp64.read ) + { + set_user_reg(regs, cp64.reg1, x & 0xffffffff); + set_user_reg(regs, cp64.reg2, x >> 32); + } + + return ret; +} + +#ifdef CONFIG_ARM_64 static inline bool vreg_emulate_sysreg32(struct cpu_user_regs *regs, union hsr hsr, - vreg_sysreg32_fn_t fn) + vreg_reg32_fn_t fn) { struct hsr_sysreg sysreg = hsr.sysreg; uint32_t r = 0; @@ -29,7 +83,7 @@ static inline bool vreg_emulate_sysreg32(struct cpu_user_regs *regs, union hsr h } static inline bool vreg_emulate_sysreg64(struct cpu_user_regs *regs, union hsr hsr, - vreg_sysreg64_fn_t fn) + vreg_reg64_fn_t fn) { struct hsr_sysreg sysreg = hsr.sysreg; /*