From patchwork Wed Jul 27 17:09:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 72906 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp424511qga; Wed, 27 Jul 2016 10:12:50 -0700 (PDT) X-Received: by 10.36.139.67 with SMTP id g64mr33754309ite.75.1469639567567; Wed, 27 Jul 2016 10:12:47 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id a4si8280343ioe.131.2016.07.27.10.12.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jul 2016 10:12:47 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSSLC-0004KJ-Nm; Wed, 27 Jul 2016 17:09:54 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSSLB-0004Jd-Kp for xen-devel@lists.xen.org; Wed, 27 Jul 2016 17:09:53 +0000 Received: from [193.109.254.147] by server-7.bemta-14.messagelabs.com id 89/83-06589-1EAE8975; Wed, 27 Jul 2016 17:09:53 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTffBqxn hBhu+Slks+biYxYHR4+ju30wBjFGsmXlJ+RUJrBkTL71lKmgQr9hw+x5LA+MuwS5GTg4hgU2M EquXaEPYpxkl7vxJALHZBDQl7nz+xARiiwhIS1z7fJmxi5GLg1mgjVFi7eypjCAJYYFEiekH3 7OD2CwCqhJzZrcBxTk4eAWcJR73RoKEJQTkJE4em8wKYnMKuEh0XG9jgtjlLDFn7z7WCYzcCx gZVjFqFKcWlaUW6RoZ6yUVZaZnlOQmZuboGhqa6OWmFhcnpqfmJCYV6yXn525iBHq3noGBcQf jrON+hxglOZiURHm5ns0IF+JLyk+pzEgszogvKs1JLT7EKMPBoSTBW/cSKCdYlJqeWpGWmQMM M5i0BAePkgjvBpA0b3FBYm5xZjpE6hSjopQ4rxxIQgAkkVGaB9cGC+1LjLJSwryMDAwMQjwFq UW5mSWo8q8YxTkYlYR554NM4cnMK4Gb/gpoMRPQ4uJYsMUliQgpqQbG8HvpH7L02pS538U/Mv p2Tmyz+iIft1UzUoUNfkeWdV57dUuye+m9Mus5256uzvXbpf3OiEU53jSp9dDsnsOKWYxxZ1+ wfL517PQZc2nvT0kHlvq6b1LWclzhNfXLloYDGXd48p5cYfnP8OXHCmPVn1vT1h4q5tefoe57 RV7u3ZyZkuddBY6eUGIpzkg01GIuKk4EAAmQnvBoAgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-4.tower-27.messagelabs.com!1469639391!55464211!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.77; banners=-,-,- X-VirusChecked: Checked Received: (qmail 57396 invoked from network); 27 Jul 2016 17:09:52 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-4.tower-27.messagelabs.com with SMTP; 27 Jul 2016 17:09:52 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F319B434; Wed, 27 Jul 2016 10:11:07 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.218.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7FF4D3F213; Wed, 27 Jul 2016 10:09:50 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 27 Jul 2016 18:09:37 +0100 Message-Id: <1469639378-9244-6-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1469639378-9244-1-git-send-email-julien.grall@arm.com> References: <1469639378-9244-1-git-send-email-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, steve.capper@arm.com, wei.chen@linaro.org Subject: [Xen-devel] [PATCH v2 5/6] xen/arm: traps: Avoid unnecessary VA -> IPA translation in abort handlers X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Translating a VA to a IPA is expensive. Currently, Xen is assuming that HPFAR_EL2 is only valid when the stage-2 data/instruction abort happened during a translation table walk of a first stage translation (i.e S1PTW is set). However, based on the ARM ARM (D7.2.34 in DDI 0487A.j), the register is also valid when the data/instruction abort occured for a translation fault. With this change, the VA -> IPA translation will only happen for permission faults that are not related to a translation table of a first stage translation. Signed-off-by: Julien Grall --- Changes in v2: - Use fsc in the switch in do_trap_data_abort_guest --- xen/arch/arm/traps.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ea105f2..83a30fa 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2382,13 +2382,28 @@ static inline paddr_t get_faulting_ipa(vaddr_t gva) return ipa; } +static inline bool hpfar_is_valid(bool s1ptw, uint8_t fsc) +{ + /* + * HPFAR is valid if one of the following cases are true: + * 1. the stage 2 fault happen during a stage 1 page table walk + * (the bit ESR_EL2.S1PTW is set) + * 2. the fault was due to a translation fault + * + * Note that technically HPFAR is valid for other cases, but they + * are currently not supported by Xen. + */ + return s1ptw || (fsc == FSC_FLT_TRANS); +} + static void do_trap_instr_abort_guest(struct cpu_user_regs *regs, const union hsr hsr) { int rc; register_t gva = READ_SYSREG(FAR_EL2); + uint8_t fsc = hsr.iabt.ifsc & ~FSC_LL_MASK; - switch ( hsr.iabt.ifsc & ~FSC_LL_MASK ) + switch ( fsc ) { case FSC_FLT_PERM: { @@ -2399,7 +2414,7 @@ static void do_trap_instr_abort_guest(struct cpu_user_regs *regs, .kind = hsr.iabt.s1ptw ? npfec_kind_in_gpt : npfec_kind_with_gla }; - if ( hsr.iabt.s1ptw ) + if ( hpfar_is_valid(hsr.iabt.s1ptw, fsc) ) gpa = get_faulting_ipa(gva); else { @@ -2434,6 +2449,7 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs, const struct hsr_dabt dabt = hsr.dabt; int rc; mmio_info_t info; + uint8_t fsc = hsr.dabt.dfsc & ~FSC_LL_MASK; info.dabt = dabt; #ifdef CONFIG_ARM_32 @@ -2442,7 +2458,7 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs, info.gva = READ_SYSREG64(FAR_EL2); #endif - if ( dabt.s1ptw ) + if ( hpfar_is_valid(hsr.iabt.s1ptw, fsc) ) info.gpa = get_faulting_ipa(info.gva); else { @@ -2451,7 +2467,7 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs, return; /* Try again */ } - switch ( dabt.dfsc & ~FSC_LL_MASK ) + switch ( fsc ) { case FSC_FLT_PERM: {