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[192.237.175.120]) by mx.google.com with ESMTPS id 199si27614508itb.51.2016.07.27.07.01.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jul 2016 07:01:27 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSPMF-0006Ky-Tn; Wed, 27 Jul 2016 13:58:47 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSPME-0006JI-KA for xen-devel@lists.xen.org; Wed, 27 Jul 2016 13:58:46 +0000 Received: from [193.109.254.147] by server-13.bemta-14.messagelabs.com id 9C/6B-01541-51EB8975; Wed, 27 Jul 2016 13:58:45 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTVd034x wgztX+C2WfFzM4sDocXT3b6YAxijWzLyk/IoE1ozv17cyFlzjqFg/cx97A2M/excjF4eQwEZG iVv9N1ggnNOMErs6frF2MXJysAloStz5/IkJxBYRkJa49vkyI4jNLLCQUeLt7pAuRg4OYYEQi YsNZiBhFgFViZOzloO18go4S3S3/2UGsSUE5CROHpsMFucUcJHovXQJbIwQUM2ZvxtZJzByL2 BkWMWoUZxaVJZapGtkppdUlJmeUZKbmJmja2hoopebWlycmJ6ak5hUrJecn7uJEejfegYGxh2 M/Zf9DjFKcjApifIucpwRLsSXlJ9SmZFYnBFfVJqTWnyIUYaDQ0mC9+YeoJxgUWp6akVaZg4w 0GDSEhw8SiK8M3cDpXmLCxJzizPTIVKnGBWlxHl7QfoEQBIZpXlwbbDgvsQoKyXMy8jAwCDEU 5BalJtZgir/ilGcg1FJmLcOZApPZl4J3PRXQIuZgBYXx4ItLklESEk1MJacV9+Z/j96U7yssg eL7rJA5QmCVT6fJCoL9p/lkz+aHXuhU5zjQsRsSdd7rv19Ln4uh4t3rOFzmXR0v1W+QXrVE39 ppezr6me9jU9cFvyR6nFou19GLP8vTSVtzcwNNhL5ye84Hv+xaov+zz9jM0eDsEF3YfVL5WKO I32BDSc9spIdLfcosRRnJBpqMRcVJwIAC9NLtWkCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-5.tower-27.messagelabs.com!1469627924!56277191!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.77; banners=-,-,- X-VirusChecked: Checked Received: (qmail 9124 invoked from network); 27 Jul 2016 13:58:45 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-27.messagelabs.com with SMTP; 27 Jul 2016 13:58:45 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C49BF2F; Wed, 27 Jul 2016 07:00:00 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.218.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 487A43F25F; Wed, 27 Jul 2016 06:58:43 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 27 Jul 2016 14:58:26 +0100 Message-Id: <1469627910-3902-6-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1469627910-3902-1-git-send-email-julien.grall@arm.com> References: <1469627910-3902-1-git-send-email-julien.grall@arm.com> Cc: sstabellini@kernel.org, steve.capper@arm.com, Julien Grall , shannon.zhao@linaro.org, shankerd@codeaurora.org, wei.chen@linaro.org Subject: [Xen-devel] [PATCH v3 5/9] xen/arm: gic: Document how gic_set_irq_type should be called X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Changing the value of Int_config is UNPREDICTABLE when the corresponding interrupt is not disabled. The driver is assuming the interrupt will be disabled by the caller of gic_set_irq_type. Add an ASSERT to ensure it. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Add Stefano's acked-by --- xen/arch/arm/gic.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index b9371a7..72bb885 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -96,8 +96,14 @@ void gic_restore_state(struct vcpu *v) gic_restore_pending_irqs(v); } +/* desc->irq needs to be disabled before calling this function */ static void gic_set_irq_type(struct irq_desc *desc, unsigned int type) { + /* + * IRQ must be disabled before configuring it (see 4.3.13 in ARM IHI + * 0048B.b). We rely on the caller to do it. + */ + ASSERT(test_bit(_IRQ_DISABLED, &desc->status)); ASSERT(spin_is_locked(&desc->lock)); ASSERT(type != IRQ_TYPE_INVALID);