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[192.237.175.120]) by mx.google.com with ESMTPS id o202si1479024ito.32.2016.06.22.06.23.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Jun 2016 06:23:29 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bFi5w-00019i-JN; Wed, 22 Jun 2016 13:21:28 +0000 Received: from mail6.bemta6.messagelabs.com ([85.158.143.247]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bFi5v-00017k-Dq for xen-devel@lists.xen.org; Wed, 22 Jun 2016 13:21:27 +0000 Received: from [85.158.143.35] by server-1.bemta-6.messagelabs.com id 42/B1-09256-7D09A675; Wed, 22 Jun 2016 13:21:27 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTffahKx wg7kz9SyWfFzM4sDocXT3b6YAxijWzLyk/IoE1ozra3+xFbxUrbh/7AxjA+Nd+S5GLg4hgU2M EvvvL2SHcE4zSrQ2LWXuYuTkYBPQlLjz+RMTiC0iIC1x7fNlRpAiZoE2Rom1s6cygiSEBfwlf q7/y9rFyMHBIqAq8elYFUiYV8BF4sykC+wgtoSAnMTJY5NZQWxOAVeJ/+ebwGwhoJp1n8+zTm DkXsDIsIpRvTi1qCy1SNdYL6koMz2jJDcxM0fX0MBMLze1uDgxPTUnMalYLzk/dxMj0L8MQLC DseOf0yFGSQ4mJVFeeeWscCG+pPyUyozE4oz4otKc1OJDjDIcHEoSvK79QDnBotT01Iq0zBxg oMGkJTh4lER4I0HSvMUFibnFmekQqVOMilLivDUgCQGQREZpHlwbLLgvMcpKCfMyAh0ixFOQW pSbWYIq/4pRnINRSZhXAWQKT2ZeCdz0V0CLmYAWL+tPB1lckoiQkmpg3DNHnX3jxZTfyi+9L7 oF84a47uh5rvzw7qqi9/2xNkmzbqlobFVrn3Ly/dS0fq+qs/47Pl4yuc6TIe7dPuVY35ai1Io 9z5e6zg9IUZf4xaj0a2OvE/PWiQ6Gn1jWLC0KP/G/eVpOxo6ChV++2AdqX3R2DUk9nrWcT+uE nsqaQsmDu4T6zZ8bKLEUZyQaajEXFScCABcWYrVpAgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-2.tower-21.messagelabs.com!1466601683!6353330!3 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 51732 invoked from network); 22 Jun 2016 13:21:26 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-2.tower-21.messagelabs.com with SMTP; 22 Jun 2016 13:21:26 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D4D6938; Wed, 22 Jun 2016 06:22:13 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 27FE13F21A; Wed, 22 Jun 2016 06:21:25 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 22 Jun 2016 14:21:06 +0100 Message-Id: <1466601669-25398-7-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466601669-25398-1-git-send-email-julien.grall@arm.com> References: <1466601669-25398-1-git-send-email-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, steve.capper@arm.com, wei.chen@linaro.org Subject: [Xen-devel] [PATCH 6/9] xen/arm: Use check_workaround to handle the erratum 766422 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Currently, Xen is reading the MIDR everytime it has to check whether the processor is affected by the erratum 766422. This could take advantage of the new capability bitfields to detect whether the processor is affected at boot time. With this patch, the number of instructions to check the erratum is going down from ~13 (including 2 loads and a co-processor access) to ~6 instructions (include 1 load). Signed-off-by: Julien Grall --- xen/arch/arm/cpuerrata.c | 6 ++++++ xen/arch/arm/traps.c | 3 ++- xen/include/asm-arm/arm32/processor.h | 4 ---- xen/include/asm-arm/arm64/processor.h | 2 -- xen/include/asm-arm/cpuerrata.h | 2 ++ xen/include/asm-arm/cpufeature.h | 3 ++- xen/include/asm-arm/processor.h | 2 ++ 7 files changed, 14 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 3ac97b3..748e02e 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -17,6 +17,12 @@ is_affected_midr_range(const struct arm_cpu_capabilities *entry) } static const struct arm_cpu_capabilities arm_errata[] = { + { + /* Cortex-A15 r0p4 */ + .desc = "ARM erratum 766422", + .capability = ARM32_WORKAROUND_766422, + MIDR_RANGE(MIDR_CORTEX_A15, 0x04, 0x04), + }, #if defined(CONFIG_ARM64_ERRATUM_827319) || \ defined(CONFIG_ARM64_ERRATUM_824069) { diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 8a3fac0..785e3e9 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -47,6 +47,7 @@ #include "vtimer.h" #include #include +#include /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in @@ -2482,7 +2483,7 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs, * Erratum 766422: Thumb store translation fault to Hypervisor may * not have correct HSR Rt value. */ - if ( cpu_has_erratum_766422() && (regs->cpsr & PSR_THUMB) && dabt.write ) + if ( check_workaround_766422() && (regs->cpsr & PSR_THUMB) && dabt.write ) { rc = decode_instruction(regs, &info.dabt); if ( rc ) diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index f41644d..11366bb 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -115,10 +115,6 @@ struct cpu_user_regs #define READ_SYSREG(R...) READ_SYSREG32(R) #define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) -/* Erratum 766422: only Cortex A15 r0p4 is affected */ -#define cpu_has_erratum_766422() \ - (unlikely(current_cpu_data.midr.bits == 0x410fc0f4)) - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index fef35a5..b0726ff 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -111,8 +111,6 @@ struct cpu_user_regs #define READ_SYSREG(name) READ_SYSREG64(name) #define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) -#define cpu_has_erratum_766422() 0 - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM64_PROCESSOR_H */ diff --git a/xen/include/asm-arm/cpuerrata.h b/xen/include/asm-arm/cpuerrata.h index b9d8dfc..aaf3edd 100644 --- a/xen/include/asm-arm/cpuerrata.h +++ b/xen/include/asm-arm/cpuerrata.h @@ -40,6 +40,8 @@ static inline bool_t check_workaround_##erratum(void) \ #endif +CHECK_WORKAROUND_HELPER(766422, ARM32_WORKAROUND_766422, CONFIG_ARM_32) + #undef CHECK_WORKAROUND_HELPER #endif /* __ARM_CPUERRATA_H */ diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 78e2263..ac6eaf0 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -37,8 +37,9 @@ #define ARM64_WORKAROUND_CLEAN_CACHE 0 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 +#define ARM32_WORKAROUND_766422 2 -#define ARM_NCAPS 2 +#define ARM_NCAPS 3 #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 1708253..15bf890 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -46,9 +46,11 @@ #define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_PART_CORTEX_A15 0xC0F #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15) #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)