From patchwork Tue Jun 7 16:48:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 69556 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp2075479qgf; Tue, 7 Jun 2016 09:50:19 -0700 (PDT) X-Received: by 10.159.39.7 with SMTP id a7mr150336uaa.59.1465318217204; Tue, 07 Jun 2016 09:50:17 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id r75si6891750vke.5.2016.06.07.09.50.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Jun 2016 09:50:17 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAKBV-0000I2-Ld; Tue, 07 Jun 2016 16:48:57 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAKBT-0000H2-Sb for xen-devel@lists.xen.org; Tue, 07 Jun 2016 16:48:55 +0000 Received: from [85.158.139.211] by server-6.bemta-5.messagelabs.com id 5B/2D-14904-7FAF6575; Tue, 07 Jun 2016 16:48:55 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRWlGSWpSXmKPExsVysyfVTffbr7B wg9N3dSyWfFzM4sDocXT3b6YAxijWzLyk/IoE1oz2+a/ZCmbJVfxdfZStgfGNWBcjF4eQwEZG iX1rbrN1MXICOacZJTq2ZILYbAKaEnc+f2ICsUUEpCWufb7MCNLALDCPUeLMwp3sIAlhgWCJX z1LGEFsFgFVicYX+8HivALOEp0X74DFJQTkJE4em8wKYnMKuEi8fP6SBWKZs8SDhl3MExi5Fz AyrGLUKE4tKkst0jU010sqykzPKMlNzMzRNTQw1ctNLS5OTE/NSUwq1kvOz93ECPQwAxDsYLx 42vMQoyQHk5Io79NvYeFCfEn5KZUZicUZ8UWlOanFhxg1ODgEJpydO51JiiUvPy9VSYJ3xk+g OsGi1PTUirTMHGAIwpRKcPAoifBmvQNK8xYXJOYWZ6ZDpE4xKkqJ8+qAJARAEhmleXBtsLC/x CgrJczLCHSUEE9BalFuZgmq/CtGcQ5GJWFeD5DtPJl5JXDTXwEtZgJazPIVbHFJIkJKqoFx2u RLCRw1tdLzT2179p+tOq60/GXOi3s7Zu77eYy7ZvV78VcfdI0nad0xOCrqu909N+fNxR8TT10 z/+xxYf/C9D2Gm6wzjq8o+7X0z0o906pC67UlXXGZxmeiZdxT2rQnFAYVK2albKh5G3x/17qP kvU/+IyvtOTX3vsofC2/aFbLhRNNG9Q2KrEUZyQaajEXFScCAElq2U52AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-14.tower-206.messagelabs.com!1465318134!7284839!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 48292 invoked from network); 7 Jun 2016 16:48:54 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-14.tower-206.messagelabs.com with SMTP; 7 Jun 2016 16:48:54 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4AF922F; Tue, 7 Jun 2016 09:49:28 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8E7533F246; Tue, 7 Jun 2016 09:48:52 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 7 Jun 2016 17:48:36 +0100 Message-Id: <1465318123-3090-2-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465318123-3090-1-git-send-email-julien.grall@arm.com> References: <1465318123-3090-1-git-send-email-julien.grall@arm.com> Cc: sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com, Julien Grall , shannon.zhao@linaro.org, shankerd@codeaurora.org Subject: [Xen-devel] [RFC 1/8] xen/arm: gic: Consolidate the IRQ affinity set in a single place X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The code to set the IRQ affinity is duplicated: once in gicv{2,3}_set_properties and the other is gicv{2,3}_irq_set_affinity. Remove the code from gicv{2,3}_set_properties and call directly the affinity set helper from the common code. Signed-off-by: Julien Grall --- xen/arch/arm/gic-v2.c | 10 +--------- xen/arch/arm/gic-v3.c | 10 ---------- xen/arch/arm/gic.c | 3 ++- xen/include/asm-arm/gic.h | 1 - 4 files changed, 3 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 450755f..90b07b3 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -200,16 +200,10 @@ static unsigned int gicv2_read_irq(void) return (readl_gicc(GICC_IAR) & GICC_IA_IRQ); } -/* - * needs to be called with a valid cpu_mask, ie each cpu in the mask has - * already called gic_cpu_init - */ static void gicv2_set_irq_properties(struct irq_desc *desc, - const cpumask_t *cpu_mask, - unsigned int priority) + unsigned int priority) { uint32_t cfg, actual, edgebit; - unsigned int mask = gicv2_cpu_mask(cpu_mask); unsigned int irq = desc->irq; unsigned int type = desc->arch.type; @@ -240,8 +234,6 @@ static void gicv2_set_irq_properties(struct irq_desc *desc, IRQ_TYPE_LEVEL_HIGH; } - /* Set target CPU mask (RAZ/WI on uniprocessor) */ - writeb_gicd(mask, GICD_ITARGETSR + irq); /* Set priority */ writeb_gicd(priority, GICD_IPRIORITYR + irq); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 9910877..c936c8a 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -472,13 +472,10 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cpu) } static void gicv3_set_irq_properties(struct irq_desc *desc, - const cpumask_t *cpu_mask, unsigned int priority) { uint32_t cfg, actual, edgebit; - uint64_t affinity; void __iomem *base; - unsigned int cpu = gicv3_get_cpu_from_mask(cpu_mask); unsigned int irq = desc->irq; unsigned int type = desc->arch.type; @@ -516,13 +513,6 @@ static void gicv3_set_irq_properties(struct irq_desc *desc, IRQ_TYPE_LEVEL_HIGH; } - affinity = gicv3_mpidr_to_affinity(cpu); - /* Make sure we don't broadcast the interrupt */ - affinity &= ~GICD_IROUTER_SPI_MODE_ANY; - - if ( irq >= NR_GIC_LOCAL_IRQS ) - writeq_relaxed(affinity, (GICD + GICD_IROUTER + irq * 8)); - /* Set priority */ if ( irq < NR_GIC_LOCAL_IRQS ) writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irq); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 2bfe4de..8a1087b 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -106,7 +106,8 @@ static void gic_set_irq_properties(struct irq_desc *desc, const cpumask_t *cpu_mask, unsigned int priority) { - gic_hw_ops->set_irq_properties(desc, cpu_mask, priority); + gic_hw_ops->set_irq_properties(desc, priority); + desc->handler->set_affinity(desc, cpu_mask); } /* Program the GIC to route an interrupt to the host (i.e. Xen) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index cd97bb2..b931f98 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -331,7 +331,6 @@ struct gic_hw_operations { unsigned int (*read_irq)(void); /* Set IRQ property */ void (*set_irq_properties)(struct irq_desc *desc, - const cpumask_t *cpu_mask, unsigned int priority); /* Send SGI */ void (*send_SGI)(enum gic_sgi sgi, enum gic_sgi_mode irqmode,