From patchwork Tue Jun 7 16:06:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 69527 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp2056624qgf; Tue, 7 Jun 2016 09:08:30 -0700 (PDT) X-Received: by 10.31.62.70 with SMTP id l67mr105438vka.92.1465315692096; Tue, 07 Jun 2016 09:08:12 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 102si7317823uaq.78.2016.06.07.09.08.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Jun 2016 09:08:12 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAJWZ-0002Eo-I5; Tue, 07 Jun 2016 16:06:39 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAJWY-0002DM-9n for xen-devel@lists.xen.org; Tue, 07 Jun 2016 16:06:38 +0000 Received: from [193.109.254.147] by server-1.bemta-14.messagelabs.com id 47/AB-28808-C01F6575; Tue, 07 Jun 2016 16:06:36 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTZfnY1i 4wYQHfBZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa0b3ojcsBUdFKg42yTQwvuPvYuTiEBLYxCjx /NZZNgjnNKPE/zv32bsYOTnYBDQl7nz+xARiiwhIS1z7fJkRxGYWaGaUWHjAD8QWFnCQeHxgF 1g9i4CqxKIrb8HqeQWcJSY17gaLSwjISZw8NpkVxOYUcJFoe/CIDcQWAqpZ+quBcQIj9wJGhl WM6sWpRWWpRbrGeklFmekZJbmJmTm6hoYmermpxcWJ6ak5iUnFesn5uZsYgd5lAIIdjHf7nA8 xSnIwKYnyfn4WFi7El5SfUpmRWJwRX1Sak1p8iFGGg0NJgrfwHVBOsCg1PbUiLTMHGGYwaQkO HiUR3iyQNG9xQWJucWY6ROoUo6KUOK8OSEIAJJFRmgfXBgvtS4yyUsK8jECHCPEUpBblZpagy r9iFOdgVBLmNQOZwpOZVwI3/RXQYiagxcuuBYMsLklESEk1MB5yn6m9pH76WnFJ0/th7k/cFm 3piikvZ/CcPd9KL6n/1M3NTamHgg0ZT7inf9dZftH3/lNJU7/5ltEOOc1GWg+9D1/dFPHkOne z3m15eZFdXsoZUWYCpobBT2OCWr9Nay9V+O0UJRp09sHzvwJhvsVN/Al/plax7Ta7t3LuMkPO iD3N22+GKrEUZyQaajEXFScCAO7PAuRoAgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-15.tower-27.messagelabs.com!1465315595!46344738!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 20810 invoked from network); 7 Jun 2016 16:06:36 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-15.tower-27.messagelabs.com with SMTP; 7 Jun 2016 16:06:36 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA701434; Tue, 7 Jun 2016 09:07:09 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 63EEA3F21A; Tue, 7 Jun 2016 09:06:34 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 7 Jun 2016 17:06:10 +0100 Message-Id: <1465315583-1278-4-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465315583-1278-1-git-send-email-julien.grall@arm.com> References: <1465315583-1278-1-git-send-email-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com Subject: [Xen-devel] [PATCH v3 03/16] xen/arm: Add macros to handle the MIDR X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Add new macros to easily get different parts of the register and to check if a given MIDR match a CPU model range. The latter will be really useful to handle errata later. The macros have been imported from the header arch/arm64/include/asm/cputype.h in Linux v4.6-rc3. Also remove MIDR_MASK which is unused. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Add Stefano's acked-by --- xen/include/asm-arm/processor.h | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 284ad6a..dba9b9a 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -9,7 +9,40 @@ #include /* MIDR Main ID Register */ -#define MIDR_MASK 0xff0ffff0 +#define MIDR_REVISION_MASK 0xf +#define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK) +#define MIDR_PARTNUM_SHIFT 4 +#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) +#define MIDR_PARTNUM(midr) \ + (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) +#define MIDR_ARCHITECTURE_SHIFT 16 +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) +#define MIDR_ARCHITECTURE(midr) \ + (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) +#define MIDR_VARIANT_SHIFT 20 +#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) +#define MIDR_VARIANT(midr) \ + (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) +#define MIDR_IMPLEMENTOR_SHIFT 24 +#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_IMPLEMENTOR(midr) \ + (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) + +#define MIDR_CPU_MODEL(imp, partnum) \ + (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + +#define MIDR_CPU_MODEL_MASK \ + (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | MIDR_ARCHITECTURE_MASK) + +#define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ +({ \ + u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ + u32 _rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ + \ + _model == (model) && _rv >= (rv_min) && _rv <= (rv_max); \ +}) /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30)