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[192.237.175.120]) by mx.google.com with ESMTPS id o92si5425467qte.124.2016.06.07.09.08.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Jun 2016 09:08:08 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAJWm-0002XF-LB; Tue, 07 Jun 2016 16:06:52 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAJWk-0002NE-RA for xen-devel@lists.xen.org; Tue, 07 Jun 2016 16:06:50 +0000 Received: from [85.158.137.68] by server-4.bemta-3.messagelabs.com id 8C/EB-31933-A11F6575; Tue, 07 Jun 2016 16:06:50 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRWlGSWpSXmKPExsVysyfVTVfqY1i 4wbkdTBZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa0bv3atMBaedKh6+2cnYwPjPpIuRi0NIYCOj xOyD31kgnNOMEt9mdDN2MXJysAloStz5/IkJxBYRkJa49vkyWJxZoJlRYuEBPxBbWCBA4ueXN ywgNouAqkTzqh6wel4BF4m2M5fBbAkBOYmTxyazgticIPEHj9hAbCEBZ4mlvxoYJzByL2BkWM WoUZxaVJZapGtoqpdUlJmeUZKbmJmja2hgrJebWlycmJ6ak5hUrJecn7uJEehhBiDYwbhmu+c hRkkOJiVR3s/PwsKF+JLyUyozEosz4otKc1KLDzHKcHAoSfAWvgPKCRalpqdWpGXmAEMNJi3B waMkwpsFkuYtLkjMLc5Mh0idYtTlODb3xlomIZa8/LxUKXFeHZAiAZCijNI8uBGwsL/EKCslz MsIdJQQT0FqUW5mCar8K0ZxDkYlYV4zkCk8mXklcJteAR3BBHTEsmvBIEeUJCKkpBoYwx9yTl j8bv/bxN7lLvc8jD3ULvee32Mslnb72OlHptW3q9Ypb71bZb6pRHa9f5YFt4vl4mUvrlrxS1+ x2P/4xpt+l+jrkm+7RGbxit5bkCzupyTifu14/Q2rNs8XZl+/ea13cDRzuyV+oETNot9ga7HW p9j2Cf9ijLmkLi7bfDEtdc3M9NgSJZbijERDLeai4kQAcciSrnYCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-2.tower-31.messagelabs.com!1465315609!44175541!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23277 invoked from network); 7 Jun 2016 16:06:49 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-2.tower-31.messagelabs.com with SMTP; 7 Jun 2016 16:06:49 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 99B162F; Tue, 7 Jun 2016 09:07:23 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 159313F21A; Tue, 7 Jun 2016 09:06:47 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 7 Jun 2016 17:06:20 +0100 Message-Id: <1465315583-1278-14-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465315583-1278-1-git-send-email-julien.grall@arm.com> References: <1465315583-1278-1-git-send-email-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com Subject: [Xen-devel] [PATCH v3 13/16] xen/arm: arm64: Add Cortex-A53 cache errata workaround X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The ARM errata 819472, 827319 and 824069 define the same workaround for these hardware issues in certain Cortex-A53 parts. The cache instructions "dc cvac" and "dc cvau" need to be upgraded to "dc civac". Use the alternative framework to replace those instructions only on affected cores. Whilst the errata affect cache instructions issued at any exception level, it is not necessary to trap EL1/EL0 data cache instructions access in order to upgrade them. Indeed the data cache corruption would always be at the address used by the data cache instructions. Note that this address could point to a shared memory between guests and the hypervisors, however all the information present in it are be validated before any use. Therefore a malicious guest could only hurt itself. Note that all the guests should implement/enable the workaround for the affected cores. Signed-off-by: Julien Grall --- Changes in v3: - Remove conflict introduced whilst rebasing this series --- docs/misc/arm/silicon-errata.txt | 3 ++ xen/arch/arm/Kconfig | 71 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/arm64/cache.S | 2 ++ xen/arch/arm/cpuerrata.c | 17 ++++++++++ xen/include/asm-arm/arm64/page.h | 7 +++- xen/include/asm-arm/cpufeature.h | 4 ++- xen/include/asm-arm/processor.h | 6 ++++ 7 files changed, 108 insertions(+), 2 deletions(-) diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt index 374a63a..fe9f52e 100644 --- a/docs/misc/arm/silicon-errata.txt +++ b/docs/misc/arm/silicon-errata.txt @@ -42,4 +42,7 @@ stable hypervisors. | Implementor | Component | Erratum ID | Kconfig | +----------------+-----------------+-----------------+-------------------------+ | ARM | Cortex-A15 | #766422 | N/A | +| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | +| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | +| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | | ARM | Cortex-A57 | #852523 | N/A | diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 0141bd9..a473d9c 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -53,6 +53,77 @@ config ALTERNATIVE endmenu +menu "ARM errata workaround via the alternative framework" + depends on ALTERNATIVE + +config ARM64_ERRATUM_827319 + bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" + default y + depends on ARM_64 + help + This option adds an alternative code sequence to work around ARM + erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI + master interface and an L2 cache. + + Under certain conditions this erratum can cause a clean line eviction + to occur at the same time as another transaction to the same address + on the AMBA 5 CHI interface, which can cause data corruption if the + interconnect reorders the two transactions. + + The workaround promotes data cache clean instructions to + data cache clean-and-invalidate. + Please note that this does not necessarily enable the workaround, + as it depends on the alternative framework, which will only patch + the kernel if an affected CPU is detected. + + If unsure, say Y. + +config ARM64_ERRATUM_824069 + bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" + default y + depends on ARM_64 + help + This option adds an alternative code sequence to work around ARM + erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected + to a coherent interconnect. + + If a Cortex-A53 processor is executing a store or prefetch for + write instruction at the same time as a processor in another + cluster is executing a cache maintenance operation to the same + address, then this erratum might cause a clean cache line to be + incorrectly marked as dirty. + + The workaround promotes data cache clean instructions to + data cache clean-and-invalidate. + Please note that this option does not necessarily enable the + workaround, as it depends on the alternative framework, which will + only patch the kernel if an affected CPU is detected. + + If unsure, say Y. + +config ARM64_ERRATUM_819472 + bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" + default y + depends on ARM_64 + help + This option adds an alternative code sequence to work around ARM + erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache + present when it is connected to a coherent interconnect. + + If the processor is executing a load and store exclusive sequence at + the same time as a processor in another cluster is executing a cache + maintenance operation to the same address, then this erratum might + cause data corruption. + + The workaround promotes data cache clean instructions to + data cache clean-and-invalidate. + Please note that this does not necessarily enable the workaround, + as it depends on the alternative framework, which will only patch + the kernel if an affected CPU is detected. + + If unsure, say Y. +endmenu + source "common/Kconfig" source "drivers/Kconfig" diff --git a/xen/arch/arm/arm64/cache.S b/xen/arch/arm/arm64/cache.S index eff4e16..9a88a2b 100644 --- a/xen/arch/arm/arm64/cache.S +++ b/xen/arch/arm/arm64/cache.S @@ -19,6 +19,8 @@ * along with this program. If not, see . */ +#include + /* * dcache_line_size - get the minimum D-cache line size from the CTR register. */ diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 52d39f8..211b520 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -17,6 +17,23 @@ is_affected_midr_range(const struct arm_cpu_capabilities *entry) } static const struct arm_cpu_capabilities arm_errata[] = { +#if defined(CONFIG_ARM64_ERRATUM_827319) || \ + defined(CONFIG_ARM64_ERRATUM_824069) + { + /* Cortex-A53 r0p[012] */ + .desc = "ARM errata 827319, 824069", + .capability = ARM64_WORKAROUND_CLEAN_CACHE, + MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), + }, +#endif +#ifdef CONFIG_ARM64_ERRATUM_819472 + { + /* Cortex-A53 r0[01] */ + .desc = "ARM erratum 819472", + .capability = ARM64_WORKAROUND_CLEAN_CACHE, + MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), + }, +#endif {}, }; diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index fbdc8fb..79ef7bd 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -3,6 +3,8 @@ #ifndef __ASSEMBLY__ +#include + /* Write a pagetable entry */ static inline void write_pte(lpae_t *p, lpae_t pte) { @@ -18,7 +20,10 @@ static inline void write_pte(lpae_t *p, lpae_t pte) #define __invalidate_dcache_one(R) "dc ivac, %" #R ";" /* Inline ASM to flush dcache on register R (may be an inline asm operand) */ -#define __clean_dcache_one(R) "dc cvac, %" #R ";" +#define __clean_dcache_one(R) \ + ALTERNATIVE("dc cvac, %" #R ";", \ + "dc civac, %" #R ";", \ + ARM64_WORKAROUND_CLEAN_CACHE) \ /* Inline ASM to clean and invalidate dcache on register R (may be an * inline asm operand) */ diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index fb57295..474a778 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -35,7 +35,9 @@ #endif #define cpu_has_security (boot_cpu_feature32(security) > 0) -#define ARM_NCAPS 0 +#define ARM64_WORKAROUND_CLEAN_CACHE 0 + +#define ARM_NCAPS 1 #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index dba9b9a..5089bfd 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -44,6 +44,12 @@ _model == (model) && _rv >= (rv_min) && _rv <= (rv_max); \ }) +#define ARM_CPU_IMP_ARM 0x41 + +#define ARM_CPU_PART_CORTEX_A53 0xD03 + +#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) + /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30) #define MPIDR_UP (_AC(1,U) << _MPIDR_UP)