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[192.237.175.120]) by mx.google.com with ESMTPS id c68si14485019qga.7.2016.06.07.09.08.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Jun 2016 09:08:03 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAJWk-0002Si-3C; Tue, 07 Jun 2016 16:06:50 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAJWi-0002P2-S9 for xen-devel@lists.xen.org; Tue, 07 Jun 2016 16:06:48 +0000 Received: from [85.158.139.211] by server-10.bemta-5.messagelabs.com id 36/D7-11369-711F6575; Tue, 07 Jun 2016 16:06:47 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRWlGSWpSXmKPExsVysyfVTVf8Y1i 4QWePmMWSj4tZHBg9ju7+zRTAGMWamZeUX5HAmvH06kO2gk6Vil/nMxsY98t2MXJxCAlsZJRY M/EWK4RzmlHi2JFFzF2MnBxsApoSdz5/YgKxRQSkJa59vswIYjMLNDNKLDzgB2ILC4RLnG6cy dLFyMHBIqAq0flCGSTMK+AisfTlBRYQW0JATuLkscmsIDYnULztwSM2EFtIwFli6a8GxgmM3A sYGVYxqhenFpWlFuma6SUVZaZnlOQmZuboGhqY6uWmFhcnpqfmJCYV6yXn525iBPqWAQh2ME5 tcD7EKMnBpCTK+/lZWLgQX1J+SmVGYnFGfFFpTmrxIUYZDg4lCd7Cd0A5waLU9NSKtMwcYJDB pCU4eJREeLNA0rzFBYm5xZnpEKlTjIpS4rw6IAkBkERGaR5cGyywLzHKSgnzMgIdIsRTkFqUm 1mCKv+KUZyDUUmY1wxkCk9mXgnc9FdAi5mAFi+7FgyyuCQRISXVwBj4N4dZQzfixx3hlN85zl cvOd27Fhlie15ZTCb3K8ck3W9X1r/XX9i5hWfuDcH3/exPbqlofYueqKkW0Hi5xs/rqs3J1QF 9DxX5TljVvtzELGIVMFGlcHdtkmHxA4uwrDaVlLgyhsCgzxoVFlMlHn1o6d6j69xbrr3JeLX3 EUeT6QpWVvsFlViKMxINtZiLihMBU+lJqWcCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-10.tower-206.messagelabs.com!1465315606!26454478!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 1020 invoked from network); 7 Jun 2016 16:06:47 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-10.tower-206.messagelabs.com with SMTP; 7 Jun 2016 16:06:47 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E8BDE2F; Tue, 7 Jun 2016 09:07:20 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 667143F21A; Tue, 7 Jun 2016 09:06:45 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 7 Jun 2016 17:06:18 +0100 Message-Id: <1465315583-1278-12-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465315583-1278-1-git-send-email-julien.grall@arm.com> References: <1465315583-1278-1-git-send-email-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com Subject: [Xen-devel] [PATCH v3 11/16] xen/arm: Detect silicon revision and set cap bits accordingly X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" After each CPU has been started, we iterate through a list of CPU errata to detect CPUs which need from hypervisor code patches. For each bug there is a function which check if that a particular CPU is affected. This needs to be done on every CPUs to cover heterogenous system properly. If a certain erratum has been detected, the capability bit will be set. In the case the erratum requires code patching, this will be triggered by the call to apply_alternatives. The code is based on the file arch/arm64/kernel/cpu_errata.c in Linux v4.6-rc3. Signed-off-by: Julien Grall --- Changes in v3: - Move update_cpu_capabilities in a separate patch - Update the commit message to mention that workaround may not require code patching. Changes in v2: - Use XENLOG_INFO for the loglevel of the message --- xen/arch/arm/Makefile | 1 + xen/arch/arm/cpuerrata.c | 26 ++++++++++++++++++++++++++ xen/arch/arm/setup.c | 3 +++ xen/arch/arm/smpboot.c | 3 +++ xen/include/asm-arm/cpuerrata.h | 6 ++++++ xen/include/asm-arm/cpufeature.h | 6 ++++++ 6 files changed, 45 insertions(+) create mode 100644 xen/arch/arm/cpuerrata.c create mode 100644 xen/include/asm-arm/cpuerrata.h diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 67ccc43..a90ecf3 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -7,6 +7,7 @@ subdir-$(CONFIG_ACPI) += acpi obj-$(CONFIG_ALTERNATIVE) += alternative.o obj-y += bootfdt.o obj-y += cpu.o +obj-y += cpuerrata.o obj-y += cpufeature.o obj-y += decode.o obj-y += device.o diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c new file mode 100644 index 0000000..52d39f8 --- /dev/null +++ b/xen/arch/arm/cpuerrata.c @@ -0,0 +1,26 @@ +#include +#include +#include + +#define MIDR_RANGE(model, min, max) \ + .matches = is_affected_midr_range, \ + .midr_model = model, \ + .midr_range_min = min, \ + .midr_range_max = max + +static bool_t __maybe_unused +is_affected_midr_range(const struct arm_cpu_capabilities *entry) +{ + return MIDR_IS_CPU_MODEL_RANGE(boot_cpu_data.midr.bits, entry->midr_model, + entry->midr_range_min, + entry->midr_range_max); +} + +static const struct arm_cpu_capabilities arm_errata[] = { + {}, +}; + +void check_local_cpu_errata(void) +{ + update_cpu_capabilities(arm_errata, "enabled workaround for"); +} diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 01e2900..6e34bea 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -171,6 +172,8 @@ static void __init processor_id(void) } processor_setup(); + + check_local_cpu_errata(); } void dt_unreserved_regions(paddr_t s, paddr_t e, diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index ba83406..fdd11b5 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -317,6 +318,8 @@ void start_secondary(unsigned long boot_phys_offset, local_irq_enable(); local_abort_enable(); + check_local_cpu_errata(); + printk(XENLOG_DEBUG "CPU %u booted.\n", smp_processor_id()); startup_cpu_idle_loop(); diff --git a/xen/include/asm-arm/cpuerrata.h b/xen/include/asm-arm/cpuerrata.h new file mode 100644 index 0000000..8ffd7ba --- /dev/null +++ b/xen/include/asm-arm/cpuerrata.h @@ -0,0 +1,6 @@ +#ifndef __ARM_CPUERRATA_H +#define __ARM_CPUERRATA_H + +void check_local_cpu_errata(void); + +#endif /* __ARM_CPUERRATA_H */ diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index be2414c..fb57295 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -66,6 +66,12 @@ struct arm_cpu_capabilities { const char *desc; u16 capability; bool_t (*matches)(const struct arm_cpu_capabilities *); + union { + struct { /* To be used for eratum handling only */ + u32 midr_model; + u32 midr_range_min, midr_range_max; + }; + }; }; void update_cpu_capabilities(const struct arm_cpu_capabilities *caps,