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[192.237.175.120]) by mx.google.com with ESMTPS id a8si30064165qkj.98.2016.05.23.07.19.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 May 2016 07:19:02 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b4qg9-0003ay-3d; Mon, 23 May 2016 14:17:57 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b4qg8-0003ZD-1H for xen-devel@lists.xen.org; Mon, 23 May 2016 14:17:56 +0000 Received: from [85.158.139.211] by server-14.bemta-5.messagelabs.com id E0/67-29484-31113475; Mon, 23 May 2016 14:17:55 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRWlGSWpSXmKPExsVysyfVTVdI0Dn c4MoJXYslHxezODB6HN39mymAMYo1My8pvyKBNePapx1sBbd9K84caGZsYJzn2MXIxSEksJFR YsbJyUxdjJxAzmlGiTtr2UFsNgFNiTufP4HFRQSkJa59vswI0sAsMIdRYs2Dv8wgCWGBOImlG zawgtgsAqoSu66cYgOxeQVcJJ6uXg1WIyEgJ3Hy2GSwGk4BV4ntX84xQixzkei4tZN9AiP3Ak aGVYwaxalFZalFuoameklFmekZJbmJmTm6hgamermpxcWJ6ak5iUnFesn5uZsYgR5mAIIdjA3 bPQ8xSnIwKYnyntzhFC7El5SfUpmRWJwRX1Sak1p8iFGGg0NJgnczv3O4kGBRanpqRVpmDjDU YNISHDxKIryH+IDSvMUFibnFmekQqVOMuhzH5t5YyyTEkpeflyolzjsNZIYASFFGaR7cCFjYX 2KUlRLmZQQ6SoinILUoN7MEVf4VozgHo5Iw7xaQKTyZeSVwm14BHcEEdMRDaQeQI0oSEVJSDY w1nQFvti9zVzpeEMag+y/vbtCr+RsXFEo09k3TDtsamKfn9cqXm8Gy6VzAr6s738/IuXvFqMJ yfey5pvUTZJzsGLcyrFw8+U9EXN2qXNfv6X8uXD3+MeL6zPWyk5Yvc3vyOrBjp0ktk2hrnJ67 PHv8wknbb+pwXm6Yy/Kva2NdxY4T86rSZY2VWIozEg21mIuKEwEnvKr6dgIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-3.tower-206.messagelabs.com!1464013068!37465424!5 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.3 required=7.0 tests=MAILTO_TO_SPAM_ADDR X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 34814 invoked from network); 23 May 2016 14:17:54 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-3.tower-206.messagelabs.com with SMTP; 23 May 2016 14:17:54 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3230159; Mon, 23 May 2016 07:18:16 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DF6603F21A; Mon, 23 May 2016 07:17:52 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 23 May 2016 15:17:25 +0100 Message-Id: <1464013052-32587-9-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464013052-32587-1-git-send-email-julien.grall@arm.com> References: <1464013052-32587-1-git-send-email-julien.grall@arm.com> Cc: sstabellini@kernel.org, wei.liu2@citrix.com, steve.capper@arm.com, andre.przywara@arm.com, Julien Grall , wei.chen@linaro.org Subject: [Xen-devel] [PATCH v2 08/15] xen/arm: arm64: Add helpers to decode and encode branch instructions X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" We may need to update branch instruction when patching Xen. The code has been imported from the files arch/arm64/kernel/insn.c and arch/arm64/include/asm/insn.h in Linux v4.6. Note that only the necessary helpers have been imported. Signed-off-by: Julien Grall --- Changes in v2: - Re-sync with Linux v4.6 - Drop any reference to arm32 --- xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/insn.c | 219 +++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/arm64/insn.h | 72 +++++++++++++ xen/include/asm-arm/insn.h | 20 ++++ 4 files changed, 312 insertions(+) create mode 100644 xen/arch/arm/arm64/insn.c create mode 100644 xen/include/asm-arm/arm64/insn.h create mode 100644 xen/include/asm-arm/insn.h diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 39c6ac6..c1fa43f 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -5,6 +5,7 @@ obj-$(EARLY_PRINTK) += debug.o obj-y += domctl.o obj-y += domain.o obj-y += entry.o +obj-y += insn.o obj-y += smpboot.o obj-y += traps.o obj-y += vfp.o diff --git a/xen/arch/arm/arm64/insn.c b/xen/arch/arm/arm64/insn.c new file mode 100644 index 0000000..12b4d96 --- /dev/null +++ b/xen/arch/arm/arm64/insn.c @@ -0,0 +1,219 @@ +/* + * Based on Linux v4.6 arch/arm64/kernel.ins.c + * + * Copyright (C) 2013 Huawei Ltd. + * Author: Jiang Liu + * + * Copyright (C) 2014-2016 Zi Shen Lim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define __kprobes +#define pr_err(fmt, ...) printk(XENLOG_ERR fmt, ## __VA_ARGS__) + +bool aarch64_insn_is_branch_imm(u32 insn) +{ + return (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn) || + aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn) || + aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) || + aarch64_insn_is_bcond(insn)); +} + +static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type, + u32 *maskp, int *shiftp) +{ + u32 mask; + int shift; + + switch (type) { + case AARCH64_INSN_IMM_26: + mask = BIT(26) - 1; + shift = 0; + break; + case AARCH64_INSN_IMM_19: + mask = BIT(19) - 1; + shift = 5; + break; + case AARCH64_INSN_IMM_16: + mask = BIT(16) - 1; + shift = 5; + break; + case AARCH64_INSN_IMM_14: + mask = BIT(14) - 1; + shift = 5; + break; + case AARCH64_INSN_IMM_12: + mask = BIT(12) - 1; + shift = 10; + break; + case AARCH64_INSN_IMM_9: + mask = BIT(9) - 1; + shift = 12; + break; + case AARCH64_INSN_IMM_7: + mask = BIT(7) - 1; + shift = 15; + break; + case AARCH64_INSN_IMM_6: + case AARCH64_INSN_IMM_S: + mask = BIT(6) - 1; + shift = 10; + break; + case AARCH64_INSN_IMM_R: + mask = BIT(6) - 1; + shift = 16; + break; + default: + return -EINVAL; + } + + *maskp = mask; + *shiftp = shift; + + return 0; +} + +#define ADR_IMM_HILOSPLIT 2 +#define ADR_IMM_SIZE SZ_2M +#define ADR_IMM_LOMASK ((1 << ADR_IMM_HILOSPLIT) - 1) +#define ADR_IMM_HIMASK ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1) +#define ADR_IMM_LOSHIFT 29 +#define ADR_IMM_HISHIFT 5 + +u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn) +{ + u32 immlo, immhi, mask; + int shift; + + switch (type) { + case AARCH64_INSN_IMM_ADR: + shift = 0; + immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK; + immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK; + insn = (immhi << ADR_IMM_HILOSPLIT) | immlo; + mask = ADR_IMM_SIZE - 1; + break; + default: + if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) { + pr_err("aarch64_insn_decode_immediate: unknown immediate encoding %d\n", + type); + return 0; + } + } + + return (insn >> shift) & mask; +} + +u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, + u32 insn, u64 imm) +{ + u32 immlo, immhi, mask; + int shift; + + if (insn == AARCH64_BREAK_FAULT) + return AARCH64_BREAK_FAULT; + + switch (type) { + case AARCH64_INSN_IMM_ADR: + shift = 0; + immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT; + imm >>= ADR_IMM_HILOSPLIT; + immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT; + imm = immlo | immhi; + mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) | + (ADR_IMM_HIMASK << ADR_IMM_HISHIFT)); + break; + default: + if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) { + pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n", + type); + return AARCH64_BREAK_FAULT; + } + } + + /* Update the immediate field. */ + insn &= ~(mask << shift); + insn |= (imm & mask) << shift; + + return insn; +} + +/* + * Decode the imm field of a branch, and return the byte offset as a + * signed value (so it can be used when computing a new branch + * target). + */ +s32 aarch64_get_branch_offset(u32 insn) +{ + s32 imm; + + if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) { + imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn); + return (imm << 6) >> 4; + } + + if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) || + aarch64_insn_is_bcond(insn)) { + imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn); + return (imm << 13) >> 11; + } + + if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) { + imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn); + return (imm << 18) >> 16; + } + + /* Unhandled instruction */ + BUG(); +} + +/* + * Encode the displacement of a branch in the imm field and return the + * updated instruction. + */ +u32 aarch64_set_branch_offset(u32 insn, s32 offset) +{ + if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) + return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn, + offset >> 2); + + if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) || + aarch64_insn_is_bcond(insn)) + return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn, + offset >> 2); + + if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) + return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_14, insn, + offset >> 2); + + /* Unhandled instruction */ + BUG(); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 8 + * indent-tabs-mode: t + * End: + */ diff --git a/xen/include/asm-arm/arm64/insn.h b/xen/include/asm-arm/arm64/insn.h new file mode 100644 index 0000000..cfcdbe9 --- /dev/null +++ b/xen/include/asm-arm/arm64/insn.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2013 Huawei Ltd. + * Author: Jiang Liu + * + * Copyright (C) 2014 Zi Shen Lim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __ARCH_ARM_ARM64_INSN +#define __ARCH_ARM_ARM64_INSN + +#include +#include +#include + +enum aarch64_insn_imm_type { + AARCH64_INSN_IMM_ADR, + AARCH64_INSN_IMM_26, + AARCH64_INSN_IMM_19, + AARCH64_INSN_IMM_16, + AARCH64_INSN_IMM_14, + AARCH64_INSN_IMM_12, + AARCH64_INSN_IMM_9, + AARCH64_INSN_IMM_7, + AARCH64_INSN_IMM_6, + AARCH64_INSN_IMM_S, + AARCH64_INSN_IMM_R, + AARCH64_INSN_IMM_MAX +}; + +#define __AARCH64_INSN_FUNCS(abbr, mask, val) \ +static always_inline bool_t aarch64_insn_is_##abbr(u32 code) \ +{ return (code & (mask)) == (val); } \ +static always_inline u32 aarch64_insn_get_##abbr##_value(void) \ +{ return (val); } + +__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) +__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) +__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000) +__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000) +__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000) +__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000) +__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000) + +bool aarch64_insn_is_branch_imm(u32 insn); + +u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn); +u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, + u32 insn, u64 imm); + +s32 aarch64_get_branch_offset(u32 insn); +u32 aarch64_set_branch_offset(u32 insn, s32 offset); + +#endif /* !__ARCH_ARM_ARM64_INSN */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 8 + * indent-tabs-mode: t + * End: + */ diff --git a/xen/include/asm-arm/insn.h b/xen/include/asm-arm/insn.h new file mode 100644 index 0000000..a205ceb --- /dev/null +++ b/xen/include/asm-arm/insn.h @@ -0,0 +1,20 @@ +#ifndef __ARCH_ARM_INSN +#define __ARCH_ARM_INSN + +#include + +#if defined(CONFIG_ARM_64) +# include +#else +# error "unknown ARM variant" +#endif + +#endif /* !__ARCH_ARM_INSN */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 8 + * indent-tabs-mode: t + * End: + */