From patchwork Mon May 23 14:17:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 68377 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp112107qge; Mon, 23 May 2016 07:19:02 -0700 (PDT) X-Received: by 10.31.107.207 with SMTP id k76mr4887200vki.52.1464013141932; Mon, 23 May 2016 07:19:01 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 94si19456375uav.4.2016.05.23.07.19.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 May 2016 07:19:01 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b4qg1-0003TS-LO; Mon, 23 May 2016 14:17:49 +0000 Received: from mail6.bemta6.messagelabs.com ([85.158.143.247]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b4qg0-0003Se-9h for xen-devel@lists.xen.org; Mon, 23 May 2016 14:17:48 +0000 Received: from [85.158.143.35] by server-2.bemta-6.messagelabs.com id DE/7E-09532-B0113475; Mon, 23 May 2016 14:17:47 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTZdb0Dn c4PNTFoslHxezODB6HN39mymAMYo1My8pvyKBNeP3pMPsBUdFKl487WVvYHzH38XIxSEksJFR YuX8RiYI5zSjxJsNG5i7GDk52AQ0Je58/sQEYosISEtc+3yZEaSIWWAOo8SaB3/BioQFHCRWX 77C0sXIwcEioCqx8HwiSJhXwEVi+9TNYL0SAnISJ49NZgWxOQVcJbZ/OccIYgsB1XTc2sk+gZ F7ASPDKkb14tSistQiXSO9pKLM9IyS3MTMHF1DAzO93NTi4sT01JzEpGK95PzcTYxA/zIAwQ7 GZX+dDjFKcjApifKe3OEULsSXlJ9SmZFYnBFfVJqTWnyIUYaDQ0mCdzO/c7iQYFFqempFWmYO MNBg0hIcPEoivIf4gNK8xQWJucWZ6RCpU4yKUuK800D6BEASGaV5cG2w4L7EKCslzMsIdIgQT 0FqUW5mCar8K0ZxDkYlYd6PIFN4MvNK4Ka/AlrMBLT4obQDyOKSRISUVANj486PRlF+KwU9Kr oymKVsXvfwbz9gt+Lb73jtr2f27biwVeF53aHHOydvS3F9X7Sy4MmtqGzjxO32N9Kz7BJzJ76 YvSVQm8XJ+vGzK96t7CfXfd3/P2f6w5g4e65pYvEvU4JSTsYEi+vzlJ66sto9aauA2NQzJ+Zm /u5N8BX21/7yuOZD3nxnJZbijERDLeai4kQABx9zdGkCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-9.tower-21.messagelabs.com!1464013066!15441470!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 16271 invoked from network); 23 May 2016 14:17:46 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-9.tower-21.messagelabs.com with SMTP; 23 May 2016 14:17:46 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 664C33C; Mon, 23 May 2016 07:18:08 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 236323F21A; Mon, 23 May 2016 07:17:44 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 23 May 2016 15:17:20 +0100 Message-Id: <1464013052-32587-4-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464013052-32587-1-git-send-email-julien.grall@arm.com> References: <1464013052-32587-1-git-send-email-julien.grall@arm.com> Cc: sstabellini@kernel.org, wei.liu2@citrix.com, steve.capper@arm.com, andre.przywara@arm.com, Julien Grall , wei.chen@linaro.org Subject: [Xen-devel] [PATCH v2 03/15] xen/arm: Add macros to handle the MIDR X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Add new macros to easily get different parts of the register and to check if a given MIDR match a CPU model range. The latter will be really useful to handle errata later. The macros have been imported from the header arch/arm64/include/asm/cputype.h in Linux v4.6-rc3. Also remove MIDR_MASK which is unused. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Add Stefano's acked-by --- xen/include/asm-arm/processor.h | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 6789cd0..1b701c5 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -9,7 +9,40 @@ #include /* MIDR Main ID Register */ -#define MIDR_MASK 0xff0ffff0 +#define MIDR_REVISION_MASK 0xf +#define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK) +#define MIDR_PARTNUM_SHIFT 4 +#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) +#define MIDR_PARTNUM(midr) \ + (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) +#define MIDR_ARCHITECTURE_SHIFT 16 +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) +#define MIDR_ARCHITECTURE(midr) \ + (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) +#define MIDR_VARIANT_SHIFT 20 +#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) +#define MIDR_VARIANT(midr) \ + (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) +#define MIDR_IMPLEMENTOR_SHIFT 24 +#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_IMPLEMENTOR(midr) \ + (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) + +#define MIDR_CPU_MODEL(imp, partnum) \ + (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + +#define MIDR_CPU_MODEL_MASK \ + (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | MIDR_ARCHITECTURE_MASK) + +#define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ +({ \ + u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ + u32 _rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ + \ + _model == (model) && _rv >= (rv_min) && _rv <= (rv_max); \ +}) /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30)