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[192.237.175.120]) by mx.google.com with ESMTPS id 90si17552590uav.0.2016.05.23.07.19.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 May 2016 07:19:14 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b4qgH-0003nA-HH; Mon, 23 May 2016 14:18:05 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b4qgF-0003k0-S3 for xen-devel@lists.xen.org; Mon, 23 May 2016 14:18:03 +0000 Received: from [85.158.139.211] by server-15.bemta-5.messagelabs.com id 7B/A9-26599-B1113475; Mon, 23 May 2016 14:18:03 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRWlGSWpSXmKPExsVysyfVTVdK0Dn c4M9lbYslHxezODB6HN39mymAMYo1My8pvyKBNWPtx3+MBdONK6YtusjewHhZrYuRi0NIYCOj xI3t99ghnNOMEp+nTWHtYuTkYBPQlLjz+RMTiC0iIC1x7fNlRpAiZoE5jBJrHvxlBkkICwRJX Np3kgXEZhFQleictoAdxOYVcJVY9HIdG4gtISAncfLYZLChnEDx7V/OMYLYQgIuEh23drJPYO RewMiwilGjOLWoLLVI19BUL6koMz2jJDcxM0fX0MBULze1uDgxPTUnMalYLzk/dxMj0McMQLC DsWG75yFGSQ4mJVHekzucwoX4kvJTKjMSizPii0pzUosPMcpwcChJ8G7mdw4XEixKTU+tSMvM AQYbTFqCg0dJhPcQH1Cat7ggMbc4Mx0idYpRUUqcdxpInwBIIqM0D64NFuCXGGWlhHkZgQ4R4 ilILcrNLEGVf8UozsGoJMy7BWQKT2ZeCdz0V0CLmYAWP5R2AFlckoiQkmpgjNx2e9X2eXxL3r RUHvoWttr0h9Dj8rCfSyXn5DhPmvRhnp7+3HSpvmOrNlwsLGhsNvF7zcp7aduzLRXyWyLKXnG ZHE98/1UtpfBR4rOKy4d2vHl7MHnpzWXZKrOqCu9PnR0hVmTxqPjdRotfO+efXPLk7sUZbo1z paoOlzFsXjfrW+Hi6h9XTKWUWIozEg21mIuKEwHEnLoFawIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-3.tower-206.messagelabs.com!1464013068!37465424!10 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 36031 invoked from network); 23 May 2016 14:18:02 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-3.tower-206.messagelabs.com with SMTP; 23 May 2016 14:18:02 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2D43B59; Mon, 23 May 2016 07:18:24 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D963F3F21A; Mon, 23 May 2016 07:18:00 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 23 May 2016 15:17:30 +0100 Message-Id: <1464013052-32587-14-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464013052-32587-1-git-send-email-julien.grall@arm.com> References: <1464013052-32587-1-git-send-email-julien.grall@arm.com> Cc: sstabellini@kernel.org, wei.liu2@citrix.com, steve.capper@arm.com, andre.przywara@arm.com, Julien Grall , wei.chen@linaro.org Subject: [Xen-devel] [PATCH v2 13/15] xen/arm: arm64: Add cortex-A57 erratum 832075 workaround X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The ARM erratum 832075 applies to certain revisions of Cortex-A57, one of the workarounds is to change device loads into using load-acquire semantics. Use the alternative framework to enable the workaround only on affected cores. Whilst a guest could trigger the deadlock, it can be broken when the processor is receiving an interrupt. As the Xen scheduler will always setup a timer (firing to every 1ms to 300ms depending on the running time slice) on each processor, the deadlock would last only few milliseconds and only affects the guest time slice. Therefore a malicious guest could only hurt itself. Note that all the guests should implement/enable the workaround for the affected cores. Signed-off-by: Julien Grall --- Changes in v2: - Update the commit message to explain why it is not necessary to take care of possible deadlock from the guest. --- docs/misc/arm/silicon-errata.txt | 1 + xen/arch/arm/Kconfig | 20 ++++++++++++++++++++ xen/arch/arm/cpuerrata.c | 9 +++++++++ xen/include/asm-arm/arm64/io.h | 21 +++++++++++++++++---- xen/include/asm-arm/cpufeature.h | 3 ++- xen/include/asm-arm/processor.h | 2 ++ 6 files changed, 51 insertions(+), 5 deletions(-) diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt index 9a2983b..ab2e5bc 100644 --- a/docs/misc/arm/silicon-errata.txt +++ b/docs/misc/arm/silicon-errata.txt @@ -46,3 +46,4 @@ stable hypervisors. | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | | ARM | Cortex-A57 | #852523 | N/A | +| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index a473d9c..e26c4c8 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -122,6 +122,26 @@ config ARM64_ERRATUM_819472 the kernel if an affected CPU is detected. If unsure, say Y. + +config ARM64_ERRATUM_832075 + bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" + default y + depends on ARM_64 + help + This option adds an alternative code sequence to work around ARM + erratum 832075 on Cortex-A57 parts up to r1p2. + + Affected Cortex-A57 parts might deadlock when exclusive load/store + instructions to Write-Back memory are mixed with Device loads. + + The workaround is to promote device loads to use Load-Acquire + semantics. + Please note that this does not necessarily enable the workaround, + as it depends on the alternative framework, which will only patch + the kernel if an affected CPU is detected. + + If unsure, say Y. + endmenu source "common/Kconfig" diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 211b520..48fc87a 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -34,6 +34,15 @@ static const struct arm_cpu_capabilities arm_errata[] = { MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), }, #endif +#ifdef CONFIG_ARM64_ERRATUM_832075 + { + /* Cortex-A57 r0p0 - r1p2 */ + .desc = "ARM erratum 832075", + .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, + MIDR_RANGE(MIDR_CORTEX_A57, 0x00, + (1 << MIDR_VARIANT_SHIFT) | 2), + }, +#endif {}, }; diff --git a/xen/include/asm-arm/arm64/io.h b/xen/include/asm-arm/arm64/io.h index f80156f..30bfc78 100644 --- a/xen/include/asm-arm/arm64/io.h +++ b/xen/include/asm-arm/arm64/io.h @@ -22,6 +22,7 @@ #include #include +#include /* * Generic IO read/write. These perform native-endian accesses. @@ -49,28 +50,40 @@ static inline void __raw_writeq(u64 val, volatile void __iomem *addr) static inline u8 __raw_readb(const volatile void __iomem *addr) { u8 val; - asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr)); + asm volatile(ALTERNATIVE("ldrb %w0, [%1]", + "ldarb %w0, [%1]", + ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) + : "=r" (val) : "r" (addr)); return val; } static inline u16 __raw_readw(const volatile void __iomem *addr) { u16 val; - asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr)); + asm volatile(ALTERNATIVE("ldrh %w0, [%1]", + "ldarh %w0, [%1]", + ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) + : "=r" (val) : "r" (addr)); return val; } static inline u32 __raw_readl(const volatile void __iomem *addr) { u32 val; - asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr)); + asm volatile(ALTERNATIVE("ldr %w0, [%1]", + "ldar %w0, [%1]", + ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) + : "=r" (val) : "r" (addr)); return val; } static inline u64 __raw_readq(const volatile void __iomem *addr) { u64 val; - asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr)); + asm volatile(ALTERNATIVE("ldr %0, [%1]", + "ldar %0, [%1]", + ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) + : "=r" (val) : "r" (addr)); return val; } diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 474a778..78e2263 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -36,8 +36,9 @@ #define cpu_has_security (boot_cpu_feature32(security) > 0) #define ARM64_WORKAROUND_CLEAN_CACHE 0 +#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 -#define ARM_NCAPS 1 +#define ARM_NCAPS 2 #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 4123951..a2c0dbe 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -47,8 +47,10 @@ #define ARM_CPU_IMP_ARM 0x41 #define ARM_CPU_PART_CORTEX_A53 0xD03 +#define ARM_CPU_PART_CORTEX_A57 0xD07 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) +#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30)