From patchwork Thu May 5 16:34:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 67214 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp844609qge; Thu, 5 May 2016 09:35:39 -0700 (PDT) X-Received: by 10.55.133.193 with SMTP id h184mr15641558qkd.202.1462466139558; Thu, 05 May 2016 09:35:39 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id u126si6557693qkf.38.2016.05.05.09.35.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 May 2016 09:35:39 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ayMEZ-0001iA-6W; Thu, 05 May 2016 16:34:39 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ayMEX-0001gF-BO for xen-devel@lists.xen.org; Thu, 05 May 2016 16:34:37 +0000 Received: from [85.158.139.211] by server-5.bemta-5.messagelabs.com id 7E/7C-21979-C167B275; Thu, 05 May 2016 16:34:36 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTVemTDv c4MMMfoslHxezODB6HN39mymAMYo1My8pvyKBNePCi5qCi8IV0z65NzBO5u9i5OIQEtjIKPH5 7lJWCOc0o8Ti3l/MXYycHGwCmhJ3Pn9iArFFBKQlrn2+zAhSxCzQzCgxfdFrNpCEsIC1xIT+r SwgNouAqsT825PBmnkFXCSO33gIZksIyEmcPDaZFcTmFHCVWHp+JVi9EFDNyR2T2CYwci9gZF jFqF6cWlSWWqRrqJdUlJmeUZKbmJmja2hgqpebWlycmJ6ak5hUrJecn7uJEejdegYGxh2MTb3 OhxglOZiURHm3K2mHC/El5adUZiQWZ8QXleakFh9ilOHgUJLgXVkClBMsSk1PrUjLzAGGGUxa goNHSYR3BUiat7ggMbc4Mx0idYpRUUqcdy1IQgAkkVGaB9cGC+1LjLJSwryMDAwMQjwFqUW5m SWo8q8YxTkYlYR5t4NM4cnMK4Gb/gpoMRPQ4vdzNUEWlyQipKQaGPP3aAS7zzPic3v89uXuHc k2tzfnf9NcvXWPfOGUDb1OHrcr10YXXbmlxSj0sWT2miMH3jX1mOQsO/Xh98nlByyd8zw6Fi/ gLakWmely3PZs6EeDRXf/Crg2bjzQs0l/cfHiaYyL45dneOSvP+ryrL1JdpL1mVv3MvULk10M rm+Yqtz+cieDqJUSS3FGoqEWc1FxIgD6tittaAIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-14.tower-206.messagelabs.com!1462466075!1743623!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 31085 invoked from network); 5 May 2016 16:34:36 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-14.tower-206.messagelabs.com with SMTP; 5 May 2016 16:34:36 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D418B49; Thu, 5 May 2016 09:34:42 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 706BC3F252; Thu, 5 May 2016 09:34:34 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 5 May 2016 17:34:12 +0100 Message-Id: <1462466065-30212-4-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462466065-30212-1-git-send-email-julien.grall@arm.com> References: <1462466065-30212-1-git-send-email-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com Subject: [Xen-devel] [RFC 03/16] xen/arm: Add macros to handle the MIDR X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Add new macros to easily get different parts of the register and to check if a given MIDR match a CPU model range. The latter will be really useful to handle errata later. The macros have been imported from the header arch64/include/asm/cputype.h in Linux v4.6-rc3 Also remove MIDR_MASK which is unused. Signed-off-by: Julien Grall --- xen/include/asm-arm/processor.h | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 6789cd0..1b701c5 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -9,7 +9,40 @@ #include /* MIDR Main ID Register */ -#define MIDR_MASK 0xff0ffff0 +#define MIDR_REVISION_MASK 0xf +#define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK) +#define MIDR_PARTNUM_SHIFT 4 +#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) +#define MIDR_PARTNUM(midr) \ + (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) +#define MIDR_ARCHITECTURE_SHIFT 16 +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) +#define MIDR_ARCHITECTURE(midr) \ + (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) +#define MIDR_VARIANT_SHIFT 20 +#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) +#define MIDR_VARIANT(midr) \ + (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) +#define MIDR_IMPLEMENTOR_SHIFT 24 +#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_IMPLEMENTOR(midr) \ + (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) + +#define MIDR_CPU_MODEL(imp, partnum) \ + (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + +#define MIDR_CPU_MODEL_MASK \ + (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | MIDR_ARCHITECTURE_MASK) + +#define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ +({ \ + u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ + u32 _rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ + \ + _model == (model) && _rv >= (rv_min) && _rv <= (rv_max); \ +}) /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30)