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[192.237.175.120]) by mx.google.com with ESMTPS id o138si6542334qke.94.2016.05.05.09.35.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 May 2016 09:35:33 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ayMEq-00028q-Pp; Thu, 05 May 2016 16:34:56 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ayMEp-00025O-6G for xen-devel@lists.xen.org; Thu, 05 May 2016 16:34:55 +0000 Received: from [85.158.139.211] by server-4.bemta-5.messagelabs.com id 84/B8-17285-E267B275; Thu, 05 May 2016 16:34:54 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRWlGSWpSXmKPExsVysyfVTVevTDv c4NMkboslHxezODB6HN39mymAMYo1My8pvyKBNeP0942sBSulK66t/svWwPhHuIuRi0NIYCOj xOw3n1kgnNOMEtMfb2fuYuTkYBPQlLjz+RMTiC0iIC1x7fNlRpAiZoFmoKJFr9lAEsIC7hL/T 90GK2IRUJWY/vM3WDOvgKvE1U3rwGwJATmJk8cms4LYnEDxpedXsoDYQgIuEid3TGKbwMi9gJ FhFaNGcWpRWWqRrqGZXlJRZnpGSW5iZo6uoYGpXm5qcXFiempOYlKxXnJ+7iZGoI8ZgGAH4/n TnocYJTmYlER5tytphwvxJeWnVGYkFmfEF5XmpBYfYpTh4FCS4JUrBcoJFqWmp1akZeYAgw0m LcHBoyTCKwGS5i0uSMwtzkyHSJ1iVJQS511bApQQAElklObBtcEC/BKjrJQwLyPQIUI8BalFu ZklqPKvGMU5GJWEebVBxvNk5pXATX8FtJgJaPH7uZogi0sSEVJSDYzsXeHnVywWSXJutghfI3 xA9Z71+/O6eifdDWOdeE0W9dx+vqCzJ9iZt1fnSfbv3KWzjrP+8Po08V+h7ytV1uI5zHZHtxu dCveVYWwO3fLl+1bmC4sdVy3bEHgpZP27qkeMwhvcWE2L40p6tcT4gx3vCBxs/+oz1fzvY42C ftPrb5Nf/i8Ru67EUpyRaKjFXFScCABzOJTUawIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-15.tower-206.messagelabs.com!1462466093!26099550!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 53306 invoked from network); 5 May 2016 16:34:53 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-15.tower-206.messagelabs.com with SMTP; 5 May 2016 16:34:53 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 94EB53A; Thu, 5 May 2016 09:35:00 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 32E193F252; Thu, 5 May 2016 09:34:52 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 5 May 2016 17:34:25 +0100 Message-Id: <1462466065-30212-17-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462466065-30212-1-git-send-email-julien.grall@arm.com> References: <1462466065-30212-1-git-send-email-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com Subject: [Xen-devel] [RFC 16/16] xen/arm: arm64: Document Cortex-A57 erratum 834220 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The ARM erratum applies to certain revisions of Cortex-A57. The processor may report a Stage 2 translation fault as the result of Stage 1 fault for load crossing a page boundary when there is a permission fault or device memory fault at stage 1 and a translation fault at Stage 2. So Xen needs to check that Stage 1 translation does not generate a fault before handling the Stage 2 fault. If it is a Stage 1 translation fault, return to the guest to let the processor injecting the correct fault. Only document it as this is already the behavior of the fault handlers. Note that some optimization could be done to avoid unecessary translation fault. This is because HPFAR_EL2 is valid for more use case. For the moment, the code is left unmodified. Signed-off-by: Julien Grall --- docs/misc/arm/silicon-errata.txt | 1 + xen/arch/arm/traps.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt index ab2e5bc..1ac365d 100644 --- a/docs/misc/arm/silicon-errata.txt +++ b/docs/misc/arm/silicon-errata.txt @@ -47,3 +47,4 @@ stable hypervisors. | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | | ARM | Cortex-A57 | #852523 | N/A | | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | +| ARM | Cortex-A57 | #834220 | N/A | diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 3acdba0..bbd5309 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2396,6 +2396,21 @@ static void do_trap_instr_abort_guest(struct cpu_user_regs *regs, .kind = hsr.iabt.s1ptw ? npfec_kind_in_gpt : npfec_kind_with_gla }; + /* + * Erratum #834220: The processor may report a Stage 2 + * translation fault as the result of Stage 1 fault for load + * crossing a page boundary when there is a permission fault or + * device memory alignment fault at Stage 1 and a translation + * fault at Stage 2. + * + * So Xen needs to check that the Stage 1 translation does not + * generate a fault before handling stage 2 fault. If it is a Stage + * 1 translation fault, return to the guest to let the processor + * injecting the correct fault. + * + * XXX: This can be optimized to avoid some unecessary + * translation. + */ if ( hsr.iabt.s1ptw ) gpa = get_faulting_ipa(); else @@ -2445,6 +2460,21 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs, info.gva = READ_SYSREG64(FAR_EL2); #endif + /* + * Erratum #834220: The processor may report a Stage 2 + * translation fault as the result of Stage 1 fault for load + * crossing a page boundary when there is a permission fault or + * device memory alignment fault at Stage 1 and a translation + * fault at Stage 2. + * + * So Xen needs to check that the Stage 1 translation does not + * generate a fault before handling stage 2 fault. If it is a Stage + * 1 translation fault, return to the guest to let the processor + * injecting the correct fault. + * + * XXX: This can be optimized to avoid some unecessary + * translation. + */ if ( dabt.s1ptw ) info.gpa = get_faulting_ipa(); else