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[192.237.175.120]) by mx.google.com with ESMTPS id i64si5128410uai.213.2016.05.05.09.35.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 May 2016 09:35:57 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ayMEm-00020c-3D; Thu, 05 May 2016 16:34:52 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ayMEl-0001yY-Ba for xen-devel@lists.xen.org; Thu, 05 May 2016 16:34:51 +0000 Received: from [85.158.139.211] by server-1.bemta-5.messagelabs.com id 9F/B6-32266-A267B275; Thu, 05 May 2016 16:34:50 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRWlGSWpSXmKPExsVysyfVTVerTDv c4MA0foslHxezODB6HN39mymAMYo1My8pvyKBNWPbu71MBZ0uFRuP9zA2MM4x62Lk4hAS2Mgo 0XBvIiuEc5pRYufrbpYuRk4ONgFNiTufPzGB2CIC0hLXPl9mBCliFmhmlJi+6DUbSEJYwFviw sNljCA2i4CqxKGlE8HivAKuEssOTQOzJQTkJE4em8wKYnMCxZeeXwm2QEjAReLkjklsExi5Fz AyrGJUL04tKkst0jXUSyrKTM8oyU3MzNE1NDDVy00tLk5MT81JTCrWS87P3cQI9HA9AwPjDsa mXudDjJIcTEqivNuVtMOF+JLyUyozEosz4otKc1KLDzHKcHAoSfCuLAHKCRalpqdWpGXmAEMN Ji3BwaMkwrsCJM1bXJCYW5yZDpE6xajLcWzujbVMQix5+XmpUuK8a0GKBECKMkrz4EbAwv4So 6yUMC8jAwODEE9BalFuZgmq/CtGcQ5GJWHe7SBTeDLzSuA2vQI6ggnoiPdzNUGOKElESEk1MM osf1hi5Xvuoqj1kXtXz6+6+sxfQvDYo2I59U85Cw+dfLJ1008RwdbYjzxOPz48W8xbWFRccDb gRpAI+9s9RRF5vfxiAgzJ+VLxWml3HdPXVfzjmFi592T89Bi9k9E8rIWC5+NkuR4qJS+7tVPT 7ZwGy4G8z8Yz738rUbu47NZysaj04FWKf5VYijMSDbWYi4oTAT4KNy12AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-7.tower-206.messagelabs.com!1462466089!37957831!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.34; banners=-,-,- X-VirusChecked: Checked Received: (qmail 19818 invoked from network); 5 May 2016 16:34:49 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-7.tower-206.messagelabs.com with SMTP; 5 May 2016 16:34:49 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B3E3149; Thu, 5 May 2016 09:34:56 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 51C013F252; Thu, 5 May 2016 09:34:48 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 5 May 2016 17:34:22 +0100 Message-Id: <1462466065-30212-14-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462466065-30212-1-git-send-email-julien.grall@arm.com> References: <1462466065-30212-1-git-send-email-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com Subject: [Xen-devel] [RFC 13/16] xen/arm: arm64: Add Cortex-A53 cache errata workaround X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The ARM errata 819472, 827319 and 824069 define the same workaround for these hardware issues in certain Cortex-A53 parts. The cache instructions "dc cvac" and "dc cvau" need to be upgraded to "dc civac". Use the alternative framework to replace those instructions only on affected cores. Whilst the errata affect cache instructions issued at any exception level, it is not necessary to trap EL1/EL0 data cache instructions access in order to upgrade them. Indeed the data cache corruption would always be at the address used by the data cache instructions. Note that this address could point to a shared memory between guests and the hypervisors, however all the information present in it are be validated before any use. Therefore a malicious guest could only hurt itself. Note that all the guests should implement/enable the workaround for the affected cores. Signed-off-by: Julien Grall --- docs/misc/arm/silicon-errata.txt | 3 ++ xen/arch/arm/Kconfig | 71 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/arm64/cache.S | 8 ++++- xen/arch/arm/cpuerrata.c | 17 ++++++++++ xen/include/asm-arm/arm64/page.h | 7 +++- xen/include/asm-arm/cpufeature.h | 4 ++- xen/include/asm-arm/processor.h | 6 ++++ 7 files changed, 113 insertions(+), 3 deletions(-) diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt index 3f0d32b..9a2983b 100644 --- a/docs/misc/arm/silicon-errata.txt +++ b/docs/misc/arm/silicon-errata.txt @@ -42,4 +42,7 @@ stable hypervisors. | Implementor | Component | Erratum ID | Kconfig | +----------------+-----------------+-----------------+-------------------------+ | ARM | Cortex-A15 | #766422 | N/A | +| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | +| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | +| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | | ARM | Cortex-A57 | #852523 | N/A | diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 9b3e66b..6e4c769 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -53,6 +53,77 @@ config ALTERNATIVE endmenu +menu "ARM errata workaround via the alternative framework" + depends on ALTERNATIVE + +config ARM64_ERRATUM_827319 + bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" + default y + depends on ARM_64 + help + This option adds an alternative code sequence to work around ARM + erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI + master interface and an L2 cache. + + Under certain conditions this erratum can cause a clean line eviction + to occur at the same time as another transaction to the same address + on the AMBA 5 CHI interface, which can cause data corruption if the + interconnect reorders the two transactions. + + The workaround promotes data cache clean instructions to + data cache clean-and-invalidate. + Please note that this does not necessarily enable the workaround, + as it depends on the alternative framework, which will only patch + the kernel if an affected CPU is detected. + + If unsure, say Y. + +config ARM64_ERRATUM_824069 + bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" + default y + depends on ARM_64 + help + This option adds an alternative code sequence to work around ARM + erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected + to a coherent interconnect. + + If a Cortex-A53 processor is executing a store or prefetch for + write instruction at the same time as a processor in another + cluster is executing a cache maintenance operation to the same + address, then this erratum might cause a clean cache line to be + incorrectly marked as dirty. + + The workaround promotes data cache clean instructions to + data cache clean-and-invalidate. + Please note that this option does not necessarily enable the + workaround, as it depends on the alternative framework, which will + only patch the kernel if an affected CPU is detected. + + If unsure, say Y. + +config ARM64_ERRATUM_819472 + bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" + default y + depends on ARM_64 + help + This option adds an alternative code sequence to work around ARM + erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache + present when it is connected to a coherent interconnect. + + If the processor is executing a load and store exclusive sequence at + the same time as a processor in another cluster is executing a cache + maintenance operation to the same address, then this erratum might + cause data corruption. + + The workaround promotes data cache clean instructions to + data cache clean-and-invalidate. + Please note that this does not necessarily enable the workaround, + as it depends on the alternative framework, which will only patch + the kernel if an affected CPU is detected. + + If unsure, say Y. +endmenu + source "common/Kconfig" source "drivers/Kconfig" diff --git a/xen/arch/arm/arm64/cache.S b/xen/arch/arm/arm64/cache.S index bc5a8f7..1a0c80c 100644 --- a/xen/arch/arm/arm64/cache.S +++ b/xen/arch/arm/arm64/cache.S @@ -19,6 +19,8 @@ * along with this program. If not, see . */ +#include + /* * dcache_line_size - get the minimum D-cache line size from the CTR register. */ @@ -54,7 +56,11 @@ ENTRY(flush_icache_range) sub x3, x2, #1 bic x4, x0, x3 1: - dc cvau, x4 // clean D line to PoU +alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE + dc cvau, x4 +alternative_else + dc civac, x4 +alternative_endif add x4, x4, x2 cmp x4, x1 b.lo 1b diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 52d39f8..211b520 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -17,6 +17,23 @@ is_affected_midr_range(const struct arm_cpu_capabilities *entry) } static const struct arm_cpu_capabilities arm_errata[] = { +#if defined(CONFIG_ARM64_ERRATUM_827319) || \ + defined(CONFIG_ARM64_ERRATUM_824069) + { + /* Cortex-A53 r0p[012] */ + .desc = "ARM errata 827319, 824069", + .capability = ARM64_WORKAROUND_CLEAN_CACHE, + MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), + }, +#endif +#ifdef CONFIG_ARM64_ERRATUM_819472 + { + /* Cortex-A53 r0[01] */ + .desc = "ARM erratum 819472", + .capability = ARM64_WORKAROUND_CLEAN_CACHE, + MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), + }, +#endif {}, }; diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index fbdc8fb..79ef7bd 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -3,6 +3,8 @@ #ifndef __ASSEMBLY__ +#include + /* Write a pagetable entry */ static inline void write_pte(lpae_t *p, lpae_t pte) { @@ -18,7 +20,10 @@ static inline void write_pte(lpae_t *p, lpae_t pte) #define __invalidate_dcache_one(R) "dc ivac, %" #R ";" /* Inline ASM to flush dcache on register R (may be an inline asm operand) */ -#define __clean_dcache_one(R) "dc cvac, %" #R ";" +#define __clean_dcache_one(R) \ + ALTERNATIVE("dc cvac, %" #R ";", \ + "dc civac, %" #R ";", \ + ARM64_WORKAROUND_CLEAN_CACHE) \ /* Inline ASM to clean and invalidate dcache on register R (may be an * inline asm operand) */ diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index fb57295..474a778 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -35,7 +35,9 @@ #endif #define cpu_has_security (boot_cpu_feature32(security) > 0) -#define ARM_NCAPS 0 +#define ARM64_WORKAROUND_CLEAN_CACHE 0 + +#define ARM_NCAPS 1 #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 1b701c5..4123951 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -44,6 +44,12 @@ _model == (model) && _rv >= (rv_min) && _rv <= (rv_max); \ }) +#define ARM_CPU_IMP_ARM 0x41 + +#define ARM_CPU_PART_CORTEX_A53 0xD03 + +#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) + /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30) #define MPIDR_UP (_AC(1,U) << _MPIDR_UP)