From patchwork Mon Apr 18 09:29:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 66011 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp1180529qge; Mon, 18 Apr 2016 02:31:42 -0700 (PDT) X-Received: by 10.31.47.88 with SMTP id v85mr17831168vkv.118.1460971902044; Mon, 18 Apr 2016 02:31:42 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c2si13658357uac.76.2016.04.18.02.31.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Apr 2016 02:31:42 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1as5VW-0003Ih-6T; Mon, 18 Apr 2016 09:30:14 +0000 Received: from mail6.bemta6.messagelabs.com ([85.158.143.247]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1as5VU-0003Ek-Dx for xen-devel@lists.xen.org; Mon, 18 Apr 2016 09:30:12 +0000 Received: from [85.158.143.35] by server-3.bemta-6.messagelabs.com id D9/A8-07120-329A4175; Mon, 18 Apr 2016 09:30:11 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLLMWRWlGSWpSXmKPExsVysyfVTVd5pUi 4wfa37BZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8aNS2fZCpq4KzofzmRuYPzN0cXIxSEksIlR 4tb+JSwQzmlGiem7XwA5nBxsApoSdz5/YgKxRQSkJa59vswIYjMLhEm8PboFyObgEBZIlGj74 w8SZhFQlXi0/DNYOa+As8Tnr0vAxkgIyEmcPDaZdQIj5wJGhlWM6sWpRWWpRbpGeklFmekZJb mJmTm6hgZmermpxcWJ6ak5iUnFesn5uZsYgd5iAIIdjMv+Oh1ilORgUhLlnWojEi7El5SfUpm RWJwRX1Sak1p8iFGGg0NJgnfXcqCcYFFqempFWmYOMGxg0hIcPEoivK9A0rzFBYm5xZnpEKlT jIpS4rz3QRICIImM0jy4NlioXmKUlRLmZQQ6RIinILUoN7MEVf4VozgHo5Iw722QKTyZeSVw0 18BLWYCWmz9RhBkcUkiQkqqgTHvBvdyibqU5bM/iL9p2HfRy/H//u/CJ3Zf5rb5Ws3o+31/QP bXr7e9zT/r/cvYelX84ZHdkw0n994RtOp1uG1gzrHlyI7CuvfrjisZMm5Lcebf48nstf31zrc ceW/OBP5/NsfInSvNwUvVY186k/f+NbNZuMzcNLkj//9s8pH9vTn8D8s1+bNKLMUZiYZazEXF iQBX2ntRUAIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-8.tower-21.messagelabs.com!1460971810!9858270!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.28; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24699 invoked from network); 18 Apr 2016 09:30:10 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-8.tower-21.messagelabs.com with SMTP; 18 Apr 2016 09:30:10 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E478030C; Mon, 18 Apr 2016 02:28:53 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EC2F23F246; Mon, 18 Apr 2016 02:30:08 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 18 Apr 2016 10:29:51 +0100 Message-Id: <1460971791-5224-1-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 Cc: Julien Grall , sstabellini@kernel.org, wei.liu2@citrix.com Subject: [Xen-devel] [for-4.7] xen/arm: Force broadcast of TLB and instruction cache maintenance instructions X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" UP guest usually uses TLB instruction to flush only on the local CPU. The TLB flush won't be broadcasted across all the CPUs within the same innershareable domain. When the vCPU is migrated between different CPUs, it may be rescheduled to a previous CPU where the TLB has not been flushed. The TLB may contain stale entries which will result to translate incorrectly a VA to IPA or even cause TLB conflicts. To avoid a such situation, always set HCR_EL2.FB which will force the broadcast of TLB and instruction cache maintenance instructions. Cheers, Signed-off-by: Julien Grall --- This is a bug fix for Xen 4.7 and should be backported up to Xen 4.4 (first official release for ARM). Without this patch, UP guest will crash if it gets migrated on a physical CPU with stale TLBs for this guest. --- xen/arch/arm/traps.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 5e865cf..9926a57 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -124,7 +124,8 @@ void init_traps(void) /* Setup hypervisor traps */ WRITE_SYSREG(HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM| - HCR_TWE|HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP, HCR_EL2); + HCR_TWE|HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB, + HCR_EL2); isb(); }