From patchwork Thu Mar 17 09:41:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 63968 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp358327lbc; Thu, 17 Mar 2016 02:54:13 -0700 (PDT) X-Received: by 10.31.162.82 with SMTP id l79mr10799113vke.76.1458208453137; Thu, 17 Mar 2016 02:54:13 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id h20si5826058vkf.172.2016.03.17.02.54.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Mar 2016 02:54:13 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1agUc2-0000eT-DT; Thu, 17 Mar 2016 09:53:02 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1agUc0-0000e2-Sl for xen-devel@lists.xen.org; Thu, 17 Mar 2016 09:53:01 +0000 Received: from [85.158.139.211] by server-2.bemta-5.messagelabs.com id 1F/F6-12342-C7E7AE65; Thu, 17 Mar 2016 09:53:00 +0000 X-Env-Sender: zhaoshenglong@huawei.com X-Msg-Ref: server-10.tower-206.messagelabs.com!1458208376!12415957!1 X-Originating-IP: [119.145.14.66] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTE5LjE0NS4xNC42NiA9PiA4NTI3\n X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23204 invoked from network); 17 Mar 2016 09:52:59 -0000 Received: from szxga03-in.huawei.com (HELO szxga03-in.huawei.com) (119.145.14.66) by server-10.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 17 Mar 2016 09:52:59 -0000 Received: from 172.24.1.48 (EHLO szxeml432-hub.china.huawei.com) ([172.24.1.48]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BYG52640; Thu, 17 Mar 2016 17:42:16 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml432-hub.china.huawei.com (10.82.67.209) with Microsoft SMTP Server id 14.3.235.1; Thu, 17 Mar 2016 17:41:45 +0800 From: Shannon Zhao To: Date: Thu, 17 Mar 2016 17:41:02 +0800 Message-ID: <1458207668-12012-17-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1458207668-12012-1-git-send-email-zhaoshenglong@huawei.com> References: <1458207668-12012-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.56EA7BF9.00B0, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f9f752820eeeb270973c9ff0ac655c21 Cc: julien.grall@arm.com, zhaoshenglong@huawei.com, stefano.stabellini@citrix.com, shannon.zhao@linaro.org, peter.huangpeng@huawei.com Subject: [Xen-devel] [PATCH v6 16/22] arm/acpi: Configure SPI interrupt type and route to Dom0 dynamically X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" From: Shannon Zhao Interrupt information is described in DSDT and is not available at the time of booting. Check if the interrupt is permitted to access and set the interrupt type, route it to guest dynamically only for SPI and Dom0. Signed-off-by: Parth Dixit Signed-off-by: Shannon Zhao --- v6: coding style --- xen/arch/arm/vgic.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index ee35683..39d858c 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include @@ -334,6 +336,19 @@ void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) } } +#define VGIC_ICFG_MASK(intr) (1 << ((2 * ((intr) % 16)) + 1)) + +static inline unsigned int get_the_irq_type(struct vcpu *v, int n, int index) +{ + struct vgic_irq_rank *vr = vgic_get_rank(v, n); + uint32_t tr = vr->icfg[index >> 4]; + + if ( tr & VGIC_ICFG_MASK(index) ) + return IRQ_TYPE_EDGE_BOTH; + else + return IRQ_TYPE_LEVEL_MASK; +} + void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) { const unsigned long mask = r; @@ -342,9 +357,26 @@ void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) unsigned long flags; int i = 0; struct vcpu *v_target; + struct domain *d = v->domain; + int ret; while ( (i = find_next_bit(&mask, 32, i)) < 32 ) { irq = i + (32 * n); + /* Set the irq type and route it to guest only for SPI and Dom0 */ + if( irq_access_permitted(d, irq) && is_hardware_domain(d) && + ( irq >= 32 ) && ( !acpi_disabled ) ) + { + ret = irq_set_spi_type(irq, get_the_irq_type(v, n, i)); + if ( ret ) + printk(XENLOG_WARNING "The irq type is not correct\n"); + + vgic_reserve_virq(d, irq); + + ret = route_irq_to_guest(d, irq, irq, NULL); + if ( ret ) + printk(XENLOG_ERR "Unable to route IRQ %u to domain %u\n", + irq, d->domain_id); + } v_target = __vgic_get_target_vcpu(v, irq); p = irq_to_pending(v_target, irq); set_bit(GIC_IRQ_GUEST_ENABLED, &p->status);